Age | Commit message (Expand) | Author |
---|---|---|
2022-09-05 | honestly i don't know what I did | jjsuperpower |
2022-09-05 | moveing file around | jjsuperpower |
2022-09-05 | updated testbench format | jjsuperpower |
2022-09-05 | Restructuring and organizing | jjsuperpower |
2022-08-30 | reorganized hdl | jjsuperpower |
2022-08-29 | fixed parity check | jjsuperpower |
2022-08-27 | register partially tested | jjsuperpower |
2022-08-27 | moved interupt control outside reg | jjsuperpower |
2022-08-27 | coded but not tested Register file | jjsuperpower |
2022-08-24 | Update ALU, added more ops | jjsuperpower |
2022-08-21 | minor change | jjsuperpower |
2022-08-21 | basic alu coded and tested | jjsuperpower |
2022-08-15 | updated ISA | jjsuperpower |
2022-08-15 | added template | jjsuperpower |
2022-08-10 | added make file | jjsuperpower |
2022-08-07 | basic shift register working | jjsuperpower |
2022-06-26 | restructured folder | jjsuperpower |
2022-06-26 | shift_reg done | jjsuperpower |
2022-06-24 | before myhdl_wraper | jjsuperpower |
2022-06-24 | combine shiftreg working | jjsuperpower |
2022-06-24 | testing multilevel convert | jjsuperpower |
2022-06-23 | update gitignore | jjsuperpower |
2022-06-23 | basic myhdl setup working | jjsuperpower |
2022-06-19 | added hdl folder | jjsuperpower |