fixed parity check

2 files changed, 20 insertions, 6 deletions

diff --git a/hdl/core.py b/hdl/core.py
index 9355bf3..2b7a977 100644
--- a/hdl/core.py
+++ b/hdl/core.py
@@ -277,7 +277,9 @@ def test_reg(filename="reg.vcd"):
         yield dut.rd_addr.eq(dut.zx.idx)    # can be anything except flg register
         yield dut.rd.eq(0xFFFF0000)         # this does not matter
         yield from step()
-        assert (yield dut.flg) == (0x0000001f ), f'ERROR: alu is not writing to flg register'
+        assert (yield dut.flg) == (yield dut.alu_flgs), f'ERROR: alu is not writing to flg register'
+
+        
 
 
     sim = Simulator(dut)
@@ -431,7 +433,7 @@ class ALU(Elaboratable):
         m.d.comb += self.out.eq(self.tmp[0:32])
         m.d.comb += self.neg.eq(self.out[31])
         m.d.comb += self.zero.eq(self.out == 0)
-        m.d.comb += self.odd.eq(self.out[0])
+        m.d.comb += self.odd.eq(self.out.xor())     # 1 if odd number of bits, 0 if even
         
         return m
 
@@ -551,6 +553,18 @@ def test_alu(filename="alu.vcd"):
         yield from sub_proc(0, 1) # add 0 to 0
         out = yield dut.zero
         assert out == 0, f'ERROR: {out} != {0}'
+
+        # test odd
+        yield dut.op.eq(AluOpCodes.add.value)
+        yield from sub_proc(0, 0xAAAAAAAA) # add 0 to 0
+        out = yield dut.odd
+        assert out == 0, f'ERROR: {out} != {0}'
+
+        # test odd
+        yield dut.op.eq(AluOpCodes.add.value)
+        yield from sub_proc(0, 0xAAAAAAAB) # add 0 to 0
+        out = yield dut.odd
+        assert out == 1, f'ERROR: {out} != {1}'
         
 
     sim = Simulator(dut)
@@ -563,8 +577,8 @@ def test_alu(filename="alu.vcd"):
 
 
 if __name__ == '__main__':
-    reg = Reg()
-    cmd(reg, test_reg)
+    # reg = Reg()
+    # cmd(reg, test_reg)
 
-    # hdl = ALU()
-    # cmd(hdl, test_alu)
+    hdl = ALU()
+    cmd(hdl, test_alu)
diff --git a/hdl/template.py b/hdl/template.py.txt
index 64f0655..64f0655 100644
--- a/hdl/template.py
+++ b/hdl/template.py.txt