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authorjjsuperpower <jjs29356@gmail.com>2022-08-07 10:37:24 -0500
committerjjsuperpower <jjs29356@gmail.com>2022-08-07 10:37:24 -0500
commit965821b9bcf018173e0a60f49382568724a5b589 (patch)
treec45af4815e8016ac6d75d4defd2971bad9c1c069 /hdl
parentb80ae3d4aa133ee170b06719d970f6c66767a709 (diff)
basic shift register working
Diffstat (limited to 'hdl')
-rw-r--r--hdl/testing/shift_reg.py100
-rw-r--r--hdl/testing/up_counter.py50
-rw-r--r--hdl/testing/up_counter_tb.py30
3 files changed, 180 insertions, 0 deletions
diff --git a/hdl/testing/shift_reg.py b/hdl/testing/shift_reg.py
new file mode 100644
index 0000000..b7c2290
--- /dev/null
+++ b/hdl/testing/shift_reg.py
@@ -0,0 +1,100 @@
+import sys
+from amaranth import *
+from amaranth.back import verilog, cxxrtl
+from amaranth.cli import main
+from amaranth.sim import Simulator, Settle, Delay
+
+BASENAME = "shift_reg"
+
+class ShiftReg(Elaboratable):
+ def __init__(self, width):
+ self.load_val = Signal(width, reset=0, reset_less=True)
+ self.load = Signal()
+ self.reg = Signal(width)
+ self.en = Signal()
+ self.right_left = Signal()
+
+ self.ports = [self.load_val, self.en, self.right_left, self.reg]
+
+ def elaborate(self, platform):
+ m = Module()
+
+ with m.If(self.load):
+ m.d.sync += self.reg.eq(self.load_val)
+ with m.Else():
+ with m.If(self.en):
+ with m.If(self.right_left):
+ m.d.sync += self.reg.eq(self.reg << 1)
+ with m.Else():
+ m.d.sync += self.reg.eq(self.reg >> 1)
+
+ return m
+
+
+def step():
+ yield
+ yield Settle()
+
+def test_shift_reg():
+ dut = ShiftReg(8)
+
+ def proc1():
+ val = 0xAB
+
+ yield dut.load_val.eq(val)
+ yield dut.en.eq(0)
+ yield dut.load.eq(1)
+ yield
+ yield Settle()
+ yield dut.load.eq(0)
+ yield dut.en.eq(1)
+
+ for _ in range(9):
+ reg_val = yield dut.reg
+ assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)} ---GOT: {hex(reg_val)}"
+ val = val >> 1
+ yield
+ yield Settle()
+
+ val = 0xBD
+ yield dut.load_val.eq(val)
+ yield dut.load.eq(1)
+ yield dut.right_left.eq(1)
+ yield
+ yield Settle()
+ yield dut.load.eq(0)
+
+ for _ in range(9):
+ reg_val = yield dut.reg
+ assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)} ---GOT: {hex(reg_val)}"
+ val = (val << 1) & 0xff
+ yield
+ yield Settle()
+
+
+
+ sim = Simulator(dut)
+ sim.add_clock(1e-6)
+ sim.add_sync_process(proc1)
+
+ with sim.write_vcd(BASENAME + '.vcd'):
+ sim.run()
+
+
+if __name__ == '__main__':
+
+ if sys.argv[1] == "sim":
+ test_shift_reg()
+ exit()
+
+ m = ShiftReg(8)
+
+ if sys.argv[1] == "v":
+ out = verilog.convert(m, ports=m.ports)
+ with open(BASENAME + '.v','w') as f:
+ f.write(out)
+
+ elif sys.argv[1] == "cc":
+ out = cxxrtl.convert(m, ports=m.ports)
+ with open(BASENAME + '.cc','w') as f:
+ f.write(out)
diff --git a/hdl/testing/up_counter.py b/hdl/testing/up_counter.py
new file mode 100644
index 0000000..050a6b0
--- /dev/null
+++ b/hdl/testing/up_counter.py
@@ -0,0 +1,50 @@
+from amaranth import *
+from amaranth.back import verilog
+
+
+class UpCounter(Elaboratable):
+ """
+ A 16-bit up counter with a fixed limit.
+
+ Parameters
+ ----------
+ limit : int
+ The value at which the counter overflows.
+
+ Attributes
+ ----------
+ en : Signal, in
+ The counter is incremented if ``en`` is asserted, and retains
+ its value otherwise.
+ ovf : Signal, out
+ ``ovf`` is asserted when the counter reaches its limit.
+ """
+
+ def __init__(self, limit):
+ self.limit = limit
+
+ # Ports
+ self.en = Signal()
+ self.ovf = Signal()
+
+ # State
+ self.count = Signal(16)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ m.d.comb += self.ovf.eq(self.count == self.limit)
+
+ with m.If(self.en):
+ with m.If(self.ovf):
+ m.d.sync += self.count.eq(0)
+ with m.Else():
+ m.d.sync += self.count.eq(self.count + 1)
+
+ return m
+
+ def to_v(self):
+ return verilog.convert(self, ports=[self.en, self.ovf])
+
+top = UpCounter(25)
+print(top.to_v()) \ No newline at end of file
diff --git a/hdl/testing/up_counter_tb.py b/hdl/testing/up_counter_tb.py
new file mode 100644
index 0000000..7c2e8d2
--- /dev/null
+++ b/hdl/testing/up_counter_tb.py
@@ -0,0 +1,30 @@
+from amaranth.sim import Simulator
+from up_counter import UpCounter
+
+dut = UpCounter(25)
+
+
+def bench():
+ # Disabled counter should not overflow.
+ yield dut.en.eq(0)
+ for _ in range(30):
+ yield
+ assert not (yield dut.ovf)
+
+ # Once enabled, the counter should overflow in 25 cycles.
+ yield dut.en.eq(1)
+ for _ in range(25):
+ yield
+ assert not (yield dut.ovf)
+ yield
+ assert (yield dut.ovf)
+
+ # The overflow should clear in one cycle.
+ yield
+ assert not (yield dut.ovf)
+
+sim = Simulator(dut)
+sim.add_clock(1e-6) # 1 MHz
+sim.add_sync_process(bench)
+with sim.write_vcd("up_counter.vcd"):
+ sim.run() \ No newline at end of file