updated ISA

2 files changed, 41 insertions, 1 deletions

diff --git a/hdl/core.py b/hdl/core.py
new file mode 100644
index 0000000..6ef02fb
--- /dev/null
+++ b/hdl/core.py
@@ -0,0 +1,40 @@
+from amaranth import *
+from amaranth.sim import Simulator, Settle, Delay
+
+from utils import cmd
+
+class Template(Elaboratable):
+    def __init__(self):
+        ...
+
+        self.ports = [...]
+
+    def elaborate(self, platform):
+        m = Module()
+
+        ...
+
+        return m
+
+
+
+        
+
+def test(filename="out.vcd"):
+    dut = ...
+
+    def proc1():
+        ...
+
+
+    sim = Simulator(dut)
+    sim.add_clock(1e-6)
+    sim.add_sync_process(proc1)
+    
+    with sim.write_vcd(filename):
+        sim.run()
+
+
+if __name__ == '__main__':
+    shift_reg = Template(...)
+    cmd(shift_reg, test)
\ No newline at end of file
diff --git a/hdl/template.py b/hdl/template.py
index 5df554c..64f0655 100644
--- a/hdl/template.py
+++ b/hdl/template.py
@@ -32,5 +32,5 @@ def test(filename="out.vcd"):
 
 
 if __name__ == '__main__':
-    shift_reg = Template(8)
+    shift_reg = Template(...)
     cmd(shift_reg, test)
\ No newline at end of file