added make file

5 files changed, 126 insertions, 24 deletions

diff --git a/hdl/testing/shift_reg.py b/hdl/shift_reg.py
index b7c2290..dedc56b 100644
--- a/hdl/testing/shift_reg.py
+++ b/hdl/shift_reg.py
@@ -1,13 +1,16 @@
 import sys
+from wsgiref.util import shift_path_info
 from amaranth import *
 from amaranth.back import verilog, cxxrtl
 from amaranth.cli import main
 from amaranth.sim import Simulator, Settle, Delay
 
-BASENAME = "shift_reg"
+from utils import cmd
 
 class ShiftReg(Elaboratable):
     def __init__(self, width):
+        self.name = "shift_reg"
+
         self.load_val = Signal(width, reset=0, reset_less=True)
         self.load = Signal()
         self.reg = Signal(width)
@@ -30,12 +33,7 @@ class ShiftReg(Elaboratable):
 
         return m
 
-
-def step():
-    yield
-    yield Settle()
-
-def test_shift_reg():
+def test_shift_reg(filename="out.vcd"):
     dut = ShiftReg(8)
 
     def proc1():
@@ -77,24 +75,10 @@ def test_shift_reg():
     sim.add_clock(1e-6)
     sim.add_sync_process(proc1)
     
-    with sim.write_vcd(BASENAME + '.vcd'):
+    with sim.write_vcd(filename):
         sim.run()
 
 
 if __name__ == '__main__':
-
-    if sys.argv[1] == "sim":
-        test_shift_reg()
-        exit()
-
-    m = ShiftReg(8)
-
-    if sys.argv[1] == "v":
-        out = verilog.convert(m, ports=m.ports)
-        with open(BASENAME + '.v','w') as f:
-            f.write(out)
-    
-    elif sys.argv[1] == "cc":
-        out = cxxrtl.convert(m, ports=m.ports)
-        with open(BASENAME + '.cc','w') as f:
-            f.write(out)
+    shift_reg = ShiftReg(8)
+    cmd(shift_reg, test_shift_reg)
\ No newline at end of file
diff --git a/hdl/testing/async_reset.py b/hdl/testing/async_reset.py
new file mode 100644
index 0000000..4760df7
--- /dev/null
+++ b/hdl/testing/async_reset.py
@@ -0,0 +1,21 @@
+from amaranth import *
+from amaranth.cli import main
+
+
+class ClockDivisor(Elaboratable):
+    def __init__(self, factor):
+        self.v = Signal(factor)
+        self.o = Signal()
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.sync += self.v.eq(self.v + 1)
+        m.d.comb += self.o.eq(self.v[-1])
+        return m
+
+
+if __name__ == "__main__":
+    m = Module()
+    m.domains.sync = sync = ClockDomain("sync", async_reset=True)
+    m.submodules.ctr = ctr = ClockDivisor(factor=16)
+    main(m, ports=[ctr.o, sync.clk])
\ No newline at end of file
diff --git a/hdl/testing/multi_clock.py b/hdl/testing/multi_clock.py
new file mode 100644
index 0000000..e377156
--- /dev/null
+++ b/hdl/testing/multi_clock.py
@@ -0,0 +1,75 @@
+import sys
+from amaranth import *
+from amaranth.back import verilog, cxxrtl
+from amaranth.cli import main
+from amaranth.sim import Simulator, Settle, Delay
+
+BASENAME = "multi_clock"
+
+class SubM(Elaboratable):
+    def __init__(self, domain=None):
+        self.inv = Signal()
+        self.domain=domain
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.d.sync += self.inv.eq(~self.inv)
+
+        return m
+
+class top(Elaboratable):
+    def __init__(self):
+        self.sig_slow = Signal()
+        self.sig_fast = Signal()
+
+        self.div = Signal(2)
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.domains += ClockDomain('slow')
+        m.d.sync += [self.div.eq(self.div + 1)]
+        m.d.comb += ClockSignal('slow').eq(self.div[-1])
+
+        m.submodules.subm1 = SubM()
+        m.submodules.subm2 = DomainRenamer("slow")(SubM())
+
+        m.d.sync += self.sig_fast.eq(m.submodules.subm1.inv)
+        m.d.slow += self.sig_slow.eq(m.submodules.subm2.inv)
+
+        return m
+
+def test_shift_reg():
+    dut = top()
+
+    def proc1():
+        for _ in range(16):
+            yield
+            yield Settle()
+    
+    sim = Simulator(dut)
+    sim.add_clock(1e-6)
+    sim.add_sync_process(proc1)
+    
+    with sim.write_vcd(BASENAME + '.vcd'):
+        sim.run()
+
+
+if __name__ == '__main__':
+
+    if sys.argv[1] == "sim":
+        test_shift_reg()
+        exit()
+
+    # m = ShiftReg(8)
+
+    # if sys.argv[1] == "v":
+    #     out = verilog.convert(m, ports=m.ports)
+    #     with open(BASENAME + '.v','w') as f:
+    #         f.write(out)
+    
+    # elif sys.argv[1] == "cc":
+    #     out = cxxrtl.convert(m, ports=m.ports)
+    #     with open(BASENAME + '.cc','w') as f:
+    #         f.write(out)
diff --git a/hdl/testing/v b/hdl/testing/v
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/hdl/testing/v
diff --git a/hdl/utils.py b/hdl/utils.py
new file mode 100644
index 0000000..6aad95f
--- /dev/null
+++ b/hdl/utils.py
@@ -0,0 +1,22 @@
+import sys
+from typing import Callable
+from amaranth import Elaboratable
+from amaranth.back import verilog, cxxrtl
+
+def cmd(hdl, tb:Callable):
+    if len(sys.argv) <= 1:
+        exit()
+
+    if sys.argv[1] == "sim":
+        tb(sys.argv[0].replace('.py', '.vcd'))
+        exit()
+
+    if sys.argv[1] == "v":
+        out = verilog.convert(hdl, ports=hdl.ports)
+        with open(sys.argv[0].replace('.py', '.v'), 'w') as f:
+            f.write(out)
+    
+    elif sys.argv[1] == "cc":
+        out = cxxrtl.convert(hdl, ports=hdl.ports)
+        with open(sys.argv[0].replace('.py', '.cc'), 'w') as f:
+            f.write(out)
\ No newline at end of file