shift_reg done

8 files changed, 112 insertions, 297 deletions

diff --git a/hdl/testing/Makefile b/hdl/testing/Makefile
index e69de29..5e6391c 100644
--- a/hdl/testing/Makefile
+++ b/hdl/testing/Makefile
@@ -0,0 +1,12 @@
+
+HDL = shift_reg.py
+
+
+test:
+	py.test --disable-pytest-warnings -v $(HDL)
+
+test-w:
+	py.test -v $(HDL)
+
+clean: 
+	$(RM) -rf simulation/* gen_verilog/* __pycache__/* .pytest_cache/*
\ No newline at end of file
diff --git a/hdl/testing/__pycache__/constants.cpython-38.pyc b/hdl/testing/__pycache__/constants.cpython-38.pyc
deleted file mode 100644
index 764603c..0000000
--- a/hdl/testing/__pycache__/constants.cpython-38.pyc
+++ /dev/null
diff --git a/hdl/testing/__pycache__/delme.cpython-38.pyc b/hdl/testing/__pycache__/delme.cpython-38.pyc
deleted file mode 100644
index db0029e..0000000
--- a/hdl/testing/__pycache__/delme.cpython-38.pyc
+++ /dev/null
diff --git a/hdl/testing/__pycache__/shift_reg.cpython-38.pyc b/hdl/testing/__pycache__/shift_reg.cpython-38.pyc
deleted file mode 100644
index 7a2f246..0000000
--- a/hdl/testing/__pycache__/shift_reg.cpython-38.pyc
+++ /dev/null
diff --git a/hdl/testing/myhdl_wrap.py b/hdl/testing/myhdl_wrap.py
index e69de29..2e8fe4e 100644
--- a/hdl/testing/myhdl_wrap.py
+++ b/hdl/testing/myhdl_wrap.py
@@ -0,0 +1,31 @@
+import os
+from myhdl import *
+from constants import *
+
+class Myhdl_Wrapper():
+    def __init__(self):
+        self.class_name = self.__class__.__name__
+
+    def _export(self, **kargs):
+        inst = getattr(self, self.class_name)(**kargs)
+        inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}")
+        
+
+
+    # This function links myhdl to icarus verilog sim
+    def _cosim(self, **kargs): #these should have the same signals as logic(), 
+
+        iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v"
+        vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o"
+
+        os.system(iverilog_cmd)
+        return Cosimulation(vvp_cmd, **kargs)
+
+    def sim(self):
+        tb = self.tb(getattr(self, self.class_name))
+        tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim")
+        tb.run_sim()
+
+    def cosim(self):
+        tb = self.tb(self._cosim)
+        tb.run_sim()
\ No newline at end of file
diff --git a/hdl/testing/shift_reg.py b/hdl/testing/shift_reg.py
index de2ed3f..28914f1 100644
--- a/hdl/testing/shift_reg.py
+++ b/hdl/testing/shift_reg.py
@@ -1,41 +1,51 @@
+from turtle import width
 from myhdl import *
-from random import randrange
-import os
+from myhdl_wrap import Myhdl_Wrapper
 
-from constants import *
+import random
+from random import randint
 
-class ShiftReg():
+random.seed(63)
+
+class ShiftReg(Myhdl_Wrapper):
     def __init__(self):
-        self.class_name = self.__class__.__name__
+        super().__init__()
 
     # Main code, this is the actual logic
     @staticmethod
     @block
-    def ShiftReg(reset: Signal, clk: Signal, in0: Signal, out0: Signal, left_right: Signal):
+    def ShiftReg(reset: Signal, clk: Signal, load: Signal, in0: Signal, out0: Signal, left_right: Signal):
 
         width = len(out0)
 
-        @always_seq(clk.posedge, reset=reset)
+        @instance
         def shifter():
-            if not left_right:
-                out0.next[width:1] = out0[width-1:0]
-                out0.next[0] = in0
-            else:
-                out0.next[width-1:0] = out0[width:1]
-                out0.next[width-1] = in0
+            while True:
+                yield clk.posedge, reset.negedge
+
+                if not reset:
+                    out0.next = load
+                else:
+                    if not left_right:
+                        out0.next[width:1] = out0[width-1:0]
+                        out0.next[0] = in0
+                    else:
+                        out0.next[width-1:0] = out0[width:1]
+                        out0.next[width-1] = in0
 
         return shifter
 
 
     @block
     def tb(self, func):
-        reset = ResetSignal(0, 0, True)
+        reset = Signal(False)
         clk = Signal(bool(0))
-        in0 = Signal(0)
-        out0 = Signal(modbv(0)[8:])
+        load = Signal(intbv(0xA5)[8:])
+        in0 = Signal(bool(0))
+        out0 = Signal(modbv(int(load))[8:])
         left_right = Signal(bool(0))
 
-        dut = getattr(self, str(func))(reset=reset, clk=clk, in0=in0, out0=out0, left_right=left_right)
+        dut = func(reset=reset, clk=clk, load=load, in0=in0, out0=out0, left_right=left_right)
 
         @always(delay(2))
         def clock_gen():
@@ -43,63 +53,67 @@ class ShiftReg():
 
         @instance
         def monitor():
+            last_val = out0
+
             while True:
-                yield clk.posedge
+                yield clk.posedge, reset.negedge
                 yield delay(1)
-                print(bin(out0, 8))
+
+                if reset == False:
+                    assert out0 == load, "Is output is not zero at reset"
+
+                else:
+                    if not left_right:
+                        assert int(out0) == ((last_val << 1) & 0xFF) | int(in0), "Not shifting left correctly"
+                    else:
+                        assert int(out0) == ((last_val >> 1) & 0xFF) | (int(in0) << 7), "Not shifting rigth correctly"
+
+                last_val = int(out0)
 
         @instance
-        def stimulus():
+        def reset_test():
             yield clk.negedge
-            reset.next = 1
+            reset.next = True
+            while True:
+                reset.next = True
+                yield delay(randint(25, 28))
+
+                reset.next = False
+                yield delay(randint(1,4))
 
-            for i in range(9):
+        @instance
+        def stimulus():
+            for i in range(20):
                 yield clk.negedge
-                in0.next = 1
+                left_right.next = 0
+                in0.next = randint(0, 1)
 
-            for i in range(9):
+            for i in range(20):
                 yield clk.negedge
-                in0.next = 0
+                left_right.next = 1
+                in0.next = randint(0, 1)
 
             raise StopSimulation
 
-        return dut, clock_gen, monitor, stimulus
 
-    def convert(self):
-        reset = ResetSignal(0, 0, True)
+        return dut, clock_gen, monitor, stimulus, reset_test
+
+    def export(self):
+        reset = Signal(False)
         clk = Signal(bool(0))
+        load = Signal(intbv(0x00)[8:])
         in0 = Signal(bool(0))
-        out0 = Signal(modbv(0)[8:])
+        out0 = Signal(modbv(int(load))[8:])
         left_right = Signal(bool(0))
 
-        inst = self.ShiftReg(reset=reset, clk=clk, in0=in0, out0=out0, left_right=left_right)
-        inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}")
-
-
-    # This function links myhdl to icarus verilog sim
-    def _cosim(self, **kargs): #these should have the same signals as logic(), 
-
-        iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v"
-        vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o"
-
-        os.system(iverilog_cmd)
-        return Cosimulation(vvp_cmd, **kargs)
+        self._export(reset=reset, clk=clk, load=load, in0=in0, out0=out0, left_right=left_right)
 
-    def sim(self):
-        tb = self.tb(self.class_name)
-        tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim")
-        tb.run_sim()
 
-    def cosim(self):
-        tb = self.tb('_cosim')
-        tb.run_sim()
-
-
-def test_shift_reg():
+def test_shift_reg_sim():
     hdl = ShiftReg()
     hdl.sim()
-    hdl.convert()
-    hdl.cosim()
 
-
-test_shift_reg()
\ No newline at end of file
+def test_shift_reg_cosim():
+    hdl = ShiftReg()
+    hdl.export()
+    hdl.cosim()
diff --git a/hdl/testing/simulation/ShiftReg.o b/hdl/testing/simulation/ShiftReg.o
deleted file mode 100755
index 80f6349..0000000
--- a/hdl/testing/simulation/ShiftReg.o
+++ /dev/null
@@ -1,95 +0,0 @@
-#! /usr/local/bin/vvp
-:ivl_version "12.0 (devel)" "(s20150603-1545-g93397e723)";
-:ivl_delay_selection "TYPICAL";
-:vpi_time_precision - 11;
-:vpi_module "/usr/local/lib64/ivl/system.vpi";
-:vpi_module "/usr/local/lib64/ivl/vhdl_sys.vpi";
-:vpi_module "/usr/local/lib64/ivl/vhdl_textio.vpi";
-:vpi_module "/usr/local/lib64/ivl/v2005_math.vpi";
-:vpi_module "/usr/local/lib64/ivl/va_math.vpi";
-S_0x7e78f0 .scope module, "tb_ShiftReg" "tb_ShiftReg" 2 1;
- .timescale -9 -11;
-v0x7f96b0_0 .var "clk", 0 0;
-v0x7f9770_0 .var "in0", 0 0;
-v0x7f9840_0 .var "left_right", 0 0;
-v0x7f9940_0 .net "out0", 7 0, v0x7f9420_0;  1 drivers
-v0x7f9a10_0 .var "reset", 0 0;
-S_0x7e7a80 .scope module, "dut" "ShiftReg" 2 21, 3 8 0, S_0x7e78f0;
- .timescale -9 -11;
-    .port_info 0 /INPUT 1 "reset";
-    .port_info 1 /INPUT 1 "clk";
-    .port_info 2 /INPUT 1 "in0";
-    .port_info 3 /OUTPUT 8 "out0";
-    .port_info 4 /INPUT 1 "left_right";
-v0x7abed0_0 .net "clk", 0 0, v0x7f96b0_0;  1 drivers
-v0x7f9290_0 .net "in0", 0 0, v0x7f9770_0;  1 drivers
-v0x7f9350_0 .net "left_right", 0 0, v0x7f9840_0;  1 drivers
-v0x7f9420_0 .var "out0", 7 0;
-v0x7f9500_0 .net "reset", 0 0, v0x7f9a10_0;  1 drivers
-E_0x7d0b30/0 .event negedge, v0x7f9500_0;
-E_0x7d0b30/1 .event posedge, v0x7abed0_0;
-E_0x7d0b30 .event/or E_0x7d0b30/0, E_0x7d0b30/1;
-S_0x7abcf0 .scope begin, "SHIFTREG_SHIFTER" "SHIFTREG_SHIFTER" 3 27, 3 27 0, S_0x7e7a80;
- .timescale -9 -11;
-    .scope S_0x7e7a80;
-T_0 ;
-    %wait E_0x7d0b30;
-    %fork t_1, S_0x7abcf0;
-    %jmp t_0;
-    .scope S_0x7abcf0;
-t_1 ;
-    %load/vec4 v0x7f9500_0;
-    %pad/u 32;
-    %cmpi/e 0, 0, 32;
-    %jmp/0xz  T_0.0, 4;
-    %pushi/vec4 0, 0, 8;
-    %assign/vec4 v0x7f9420_0, 0;
-    %jmp T_0.1;
-T_0.0 ;
-    %load/vec4 v0x7f9350_0;
-    %nor/r;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_0.2, 8;
-    %load/vec4 v0x7f9420_0;
-    %parti/s 7, 0, 2;
-    %ix/load 4, 1, 0;
-    %ix/load 5, 0, 0;
-    %flag_set/imm 4, 0;
-    %assign/vec4/off/d v0x7f9420_0, 4, 5;
-    %load/vec4 v0x7f9290_0;
-    %ix/load 4, 0, 0;
-    %ix/load 5, 0, 0;
-    %flag_set/imm 4, 0;
-    %assign/vec4/off/d v0x7f9420_0, 4, 5;
-    %jmp T_0.3;
-T_0.2 ;
-    %load/vec4 v0x7f9420_0;
-    %parti/s 7, 1, 2;
-    %ix/load 4, 0, 0;
-    %ix/load 5, 0, 0;
-    %flag_set/imm 4, 0;
-    %assign/vec4/off/d v0x7f9420_0, 4, 5;
-    %load/vec4 v0x7f9290_0;
-    %ix/load 4, 7, 0;
-    %ix/load 5, 0, 0;
-    %flag_set/imm 4, 0;
-    %assign/vec4/off/d v0x7f9420_0, 4, 5;
-T_0.3 ;
-T_0.1 ;
-    %end;
-    .scope S_0x7e7a80;
-t_0 %join;
-    %jmp T_0;
-    .thread T_0;
-    .scope S_0x7e78f0;
-T_1 ;
-    %vpi_call 2 10 "$from_myhdl", v0x7f9a10_0, v0x7f96b0_0, v0x7f9770_0, v0x7f9840_0 {0 0 0};
-    %vpi_call 2 16 "$to_myhdl", v0x7f9940_0 {0 0 0};
-    %end;
-    .thread T_1;
-# The file index is used to find the file name in the following table.
-:file_names 4;
-    "N/A";
-    "<interactive>";
-    "./gen_verilog/tb_ShiftReg.v";
-    "./gen_verilog/ShiftReg.v";
diff --git a/hdl/testing/simulation/ShiftReg_sim.vcd b/hdl/testing/simulation/ShiftReg_sim.vcd
deleted file mode 100644
index 059b493..0000000
--- a/hdl/testing/simulation/ShiftReg_sim.vcd
+++ /dev/null
@@ -1,147 +0,0 @@
-$date
-    Fri Jun 24 11:32:38 2022
-$end
-$version
-    MyHDL 0.11
-$end
-$timescale
-    1ns
-$end
-
-$scope module tb $end
-$var reg 1 ! left_right $end
-$var reg 1 " clk $end
-$var real 1 # in0 $end
-$var reg 8 $ out0 $end
-$var reg 1 % reset $end
-$scope module ShiftReg0 $end
-$var reg 1 % reset $end
-$var reg 1 " clk $end
-$var real 1 # in0 $end
-$var reg 1 ! left_right $end
-$var reg 8 $ out0 $end
-$upscope $end
-$upscope $end
-
-$enddefinitions $end
-$dumpvars
-0!
-0"
-s0 #
-b00000000 $
-0%
-$end
-#2
-1"
-#3
-#4
-0"
-1%
-#6
-1"
-#7
-#8
-0"
-s1 #
-#10
-1"
-b00000001 $
-#11
-#12
-0"
-#14
-1"
-b00000011 $
-#15
-#16
-0"
-#18
-1"
-b00000111 $
-#19
-#20
-0"
-#22
-1"
-b00001111 $
-#23
-#24
-0"
-#26
-1"
-b00011111 $
-#27
-#28
-0"
-#30
-1"
-b00111111 $
-#31
-#32
-0"
-#34
-1"
-b01111111 $
-#35
-#36
-0"
-#38
-1"
-b11111111 $
-#39
-#40
-0"
-#42
-1"
-#43
-#44
-0"
-s0 #
-#46
-1"
-b11111110 $
-#47
-#48
-0"
-#50
-1"
-b11111100 $
-#51
-#52
-0"
-#54
-1"
-b11111000 $
-#55
-#56
-0"
-#58
-1"
-b11110000 $
-#59
-#60
-0"
-#62
-1"
-b11100000 $
-#63
-#64
-0"
-#66
-1"
-b11000000 $
-#67
-#68
-0"
-#70
-1"
-b10000000 $
-#71
-#72
-0"
-#74
-1"
-b00000000 $
-#75
-#76
-0"