minor change

1 files changed, 18 insertions, 16 deletions

diff --git a/hdl/core.py b/hdl/core.py
index a75b92e..17e2b33 100644
--- a/hdl/core.py
+++ b/hdl/core.py
@@ -1,3 +1,4 @@
+from multiprocessing import dummy
 from amaranth import *
 from amaranth.sim import Simulator, Settle, Delay
 
@@ -78,29 +79,30 @@ from utils import cmd
 #         return m
 
 class ALU(Elaboratable):
-    def __init__(self):
-        self.in1 = Signal(32)
-        self.in2 = Signal(32)
-        self.out = Signal(32)
-        self.op = Signal(4)
+    def __init__(self, sim=False):
+        self.in1 = Signal(32, reset_less=True)
+        self.in2 = Signal(32, reset_less=True)
+        self.out = Signal(32, reset_less=True)
+        self.op = Signal(4, reset_less=True)
 
-        self.tmp = Signal(33)
-        self.signed_op = Signal(1)
+        self.tmp = Signal(33, reset_less=True)
+        self.signed_op = Signal(1, reset_less=True)
 
-        self.carry = Signal(1)
-        self.overflow = Signal(1)
-        self.zero = Signal(1)
-        self.sign = Signal(1)
+        self.carry = Signal(1, reset_less=True)
+        self.overflow = Signal(1, reset_less=True)
+        self.zero = Signal(1, reset_less=True)
+        self.sign = Signal(1, reset_less=True)
 
-        self.ports = [self.in1, self.in2, self.out, self.op]
+        self.sim = sim
+        self.ports = [self.in1, self.in2, self.op, self.out, self.carry, self.overflow, self.zero, self.sign]
 
     def elaborate(self, platform=None):
         m = Module()
 
         # dummy sync for simulation only
-        if platform is None:
-            dumb = Signal()
-            m.d.sync += dumb.eq(~dumb)
+        if self.sim == True:
+            dummy = Signal()
+            m.d.sync += dummy.eq(~dummy)
 
         with m.Switch(self.op):
             with m.Case(0b0000):
@@ -139,7 +141,7 @@ class ALU(Elaboratable):
         return m
 
 def test_alu(filename="alu.vcd"):
-    dut = ALU()
+    dut = ALU(sim=True)
 
     def proc1():
         def sub_proc(val1, val2):