Restructuring and organizing

3 files changed, 159 insertions, 108 deletions

diff --git a/hdl/config.py b/hdl/config.py
new file mode 100644
index 0000000..4761c0a
--- /dev/null
+++ b/hdl/config.py
@@ -0,0 +1,8 @@
+import os
+
+ROOT_DIR = os.path.dirname(os.path.abspath(__file__))
+
+HDL_PATH = os.path.join(ROOT_DIR, 'hdl')
+VERILOG_DIR = os.path.join(ROOT_DIR, 'gen_verilog')
+CXXRTL_DIR = os.path.join(ROOT_DIR, 'gen_cxxrtl')
+VCD_DIR = os.path.join(ROOT_DIR, 'gen_vcd')
\ No newline at end of file
diff --git a/hdl/core/reg.py b/hdl/core/reg.py
index 3859dc5..b6aa3c5 100644
--- a/hdl/core/reg.py
+++ b/hdl/core/reg.py
@@ -1,51 +1,42 @@
 from amaranth import *
-from amaranth.sim import Simulator, Settle, Delay
+from amaranth.sim import Settle
 
-from hdl.utils import cmd
+from hdl.lib.in_out_buff import InOutBuff
+from hdl.utils import cmd, step, sim
 
 class Reg(Elaboratable):
     def __init__(self, **kargs):  # sim is only for modularity, does nothing for this
-        # enable write
+
+        ################ INPUTS ################
         self.wr_en = Signal(1)
+        self.stall = Signal(1)  # stall instruction pointer increment
 
-        # input and output addresses
+        self.rd = Signal(32)
         self.rd_addr = Signal(4)
         self.rs1_addr = Signal(4)
         self.rs2_addr = Signal(4)
 
-        # input and output signals
-        self.rd = Signal(32)
-        self.rs1 = Signal(32)
-        self.rs2 = Signal(32)
+        self.alu_flgs = Signal(5)   # flags from alu
 
-        #interupt enable output signal
-        self.int_en = Signal(1)
+        # these signals should be used one hot only
+        self.int_sig = Signal(1)    # unconditional interrupt
+        self.iret = Signal(1)       # return from interrupt
+        self.call = Signal(1)       # call subroutine, save return address
+        self.jump = Signal(1)       # jump, do not save return address
 
-        # alu status signals
-        self.alu_flgs = Signal(5)
 
-        # signals stack operation
-        self.stack_instr = Signal(1)
-        self.stack_down_up = Signal(1)
+        ################ OUTPUTS ################
 
-        ##################################################################
+        self.rs1 = Signal(32)   # read data 1
+        self.rs2 = Signal(32)   # read data 2
 
-        # this is the singal from the control unit, it not affected by interupt enable
-        self.int_sig = Signal(1)
-        # return from interrupt special
-        self.iret = Signal(1)
-        # jump signal to jump and link (swap ip and cs0)
-        self.jump = Signal(1)
+        self.int_en = Signal(1)     #interupt enable output signal to control unit
+        self.user_mode = Signal(1)  # user mode output signal to control unit
 
-        #################################################################
-        # None of the 3 signals above should ever be set at the same time
-        #################################################################
-        
 
-        # internal signals
-        self._user_mode = Signal(1)
-        self._sp_inc_dec = Signal(1)
+        ################ INTERNAL SIGNALS ################
         self._wr_alu_flg = Signal(1)
+        self._inc_ip = Signal(1)
 
         self.zx = Signal(32)    #0
         self.ax = Signal(32)    #1
@@ -82,39 +73,47 @@ class Reg(Elaboratable):
 
         self.reg_arr = Array(reg_list)
 
-        ports_in = [self.wr_en, self.alu_flgs, self.jump, self.int_sig, self.iret, self.stack_instr, self.stack_down_up, self.rd_addr, self.rd, self.rs1_addr, self.rs2_addr]
-        ports_out = [self.int_en, self.rs1, self.rs2, self.ip ]
+        ports_in = [self.wr_en, self.alu_flgs, self.int_sig, self.iret, self.call, self.jump, self.rd_addr, self.rd, self.rs1_addr, self.rs2_addr]
+        ports_out = [self.int_en, self.user_mode, self.rs1, self.rs2, self.ip]
         self.ports = {'in': ports_in, 'out': ports_out}
 
 
     def elaborate(self, platform=None):
         m = Module()
 
-        # user mode override
+        # output signals to control unit
         m.d.comb += self.int_en.eq(self.flg.int)
-        m.d.comb += self._user_mode.eq(self.flg.user_mode & ~self.int_sig)
-        
-        # toggle ip and cs0
-        with m.If(self.jump | self.int_sig | self.iret):
-            m.d.sync += self.cs0.eq(self.ip)
-            m.d.sync += self.ip.eq(self.cs0)
-        with m.Else():
-            m.d.sync += self.ip.eq(self.ip + 1) # increment ip only on normal operation
+        m.d.comb += self.user_mode.eq(self.flg.user_mode & ~self.int_sig)
+
+        # defualt value of internal signals
+        m.d.comb += self._wr_alu_flg.eq(1)
+        m.d.comb += self._inc_ip.eq(1)
 
         with m.If(self.int_sig):
+            m.d.comb += self._inc_ip.eq(0)
+            m.d.sync += self.ip.eq(self.rd)
+            m.d.sync += self.cs0.eq(self.ip)
             m.d.sync += self.cs1.eq(self.sp)
             m.d.sync += self.cs2.eq(self.flg)
             m.d.sync += self.flg.user_mode.eq(0)    # set to system mode or iret cannot be used
             m.d.sync += self.flg.int.eq(0)          # clear int flag, essential because another interrupt can be triggered without this
+
         with m.Elif(self.iret):
+            m.d.comb += self._inc_ip.eq(0)
+            m.d.sync += self.ip.eq(self.cs0)
             m.d.sync += self.sp.eq(self.cs1)
             m.d.sync += self.flg.eq(self.cs2)
 
-        m.d.comb += self._sp_inc_dec.eq(0)
-        m.d.comb += self._wr_alu_flg.eq(1)
+        with m.Elif(self.call):
+            m.d.comb += self._inc_ip.eq(0)
+            m.d.sync += self.ip.eq(self.rd)
+            m.d.sync += self.cs0.eq(self.ip)
+
+        with m.Elif(self.jump):
+            m.d.comb += self._inc_ip.eq(0)
+            m.d.sync += self.ip.eq(self.cs0)
 
-        # writeback setup
-        with m.If(self.wr_en):
+        with m.Elif(self.wr_en):
             with m.Switch(self.rd_addr):
                 with m.Case(self.zx.idx):    # do not write to zero register
                     pass
@@ -124,7 +123,7 @@ class Reg(Elaboratable):
 
                 with m.Case(self.flg.idx):
                     # mask top half of register to prevent writing to flags in user mode
-                    with m.If(~self._user_mode):
+                    with m.If(~self.flg.user_mode):
                         m.d.sync += self.flg.eq(self.rd)    # system mode, full control
                     with m.Else():
                         m.d.sync += self.flg.eq(Cat(self.rd[:16], self.flg[16:]))   # usermode can only effect lower 16 bits
@@ -132,56 +131,46 @@ class Reg(Elaboratable):
                     # don't update flags from alu
                     m.d.comb += self._wr_alu_flg.eq(0)
 
-                with m.Case(self.sp.idx):
-                    m.d.comb += self._sp_inc_dec.eq(1)
-                    m.d.sync += self.sp.eq(self.rd)
-
                 with m.Case():
                     m.d.sync += self.reg_arr[self.rd_addr].eq(self.rd)
 
-        with m.If(self._wr_alu_flg):
-            m.d.sync += self.flg.eq(Cat(self.alu_flgs, self.flg[len(self.alu_flgs):])) # update flags if register is not being written to
+            with m.If(self._wr_alu_flg):    # alu flags are written only if write enabled and not writing to flags register
+                m.d.sync += self.flg.eq(Cat(self.alu_flgs, self.flg[len(self.alu_flgs):]))
 
-        with m.If(~self._sp_inc_dec & self.stack_instr):
-            with m.If(self.stack_down_up):
-                m.d.sync += self.sp.eq(self.sp - 1)
-            with m.Else():
-                m.d.sync += self.sp.eq(self.sp + 1)
 
+        with m.If(self._inc_ip & ~self.stall):            # increment ip if not directly writing to ip register
+            m.d.sync += self.ip.eq(self.ip + 4)
 
+        
         ### Combination signal outputs ###
         with m.Switch(self.rs1_addr):
             with m.Case(self.flg.idx):
-                m.d.comb += self.rs1.eq(self.flg & Cat(Const(0xFFFF, 16), Repl(~self._user_mode, 16)))
+                m.d.comb += self.rs1.eq(self.flg & Cat(Const(0xFFFF, 16), Repl(~self.flg.user_mode, 16)))
             with m.Case():
                 m.d.comb += self.rs1.eq(self.reg_arr[self.rs1_addr])
 
         with m.Switch(self.rs2_addr):
             with m.Case(self.flg.idx):
-                m.d.comb += self.rs2.eq(self.flg & Cat(Const(0xFFFF, 16), Repl(~self._user_mode, 16)))
+                m.d.comb += self.rs2.eq(self.flg & Cat(Const(0xFFFF, 16), Repl(~self.flg.user_mode, 16)))
             with m.Case():
                 m.d.comb += self.rs2.eq(self.reg_arr[self.rs2_addr])
         
         return m
 
-def test_reg(filename="reg.vcd"):
-    dut = Reg(sim=True)
 
-    def init():
-        for i in range(16):
-            yield dut.reg_arr[i].eq(i)
-            yield Settle()
+#--------------------------------- TEST BENCH BELOW ---------------------------------#
 
-    def step():
-        yield Settle()  # settle comb logic before clock
-        yield           # clock edge
-        yield Settle()  # settle comb logic after clock
-        yield Delay(5e-7)   # used for debugging, change values on neg edge of clock
+def _init(dut):
+    for i in range(16):
+        yield dut.reg_arr[i].eq(i)
+        yield Settle()
 
-    def proc1():
-        yield from init()
 
-        # test combinational output
+# test combinational output
+def test_reg_comb_output():
+    dut = Reg()
+    def proc():
+        yield from _init(dut)
         for i in range(16):
             yield dut.rs1_addr.eq(i)
             yield Settle()
@@ -190,19 +179,27 @@ def test_reg(filename="reg.vcd"):
             yield dut.rs2_addr.eq(i)
             yield Settle()
             assert (yield dut.rs2) == i, f'ERROR reading {dut.reg_arr[i].name} != {i}'
+    sim(dut, proc)
 
-        # test writeback with writeback disabled
-        yield from init()
+# test writeback with writeback disabled
+def test_reg_writeback_dsb():
+    dut = Reg()
+    def proc():
+        yield from _init(dut)
         for i in range(16):
             yield dut.rd_addr.eq(i)
             yield dut.rd.eq(i + 1)
             yield from step()
             if (i != dut.ip.idx) and (i != dut.flg.idx):     # flag gets update by the alu
                 assert (yield dut.reg_arr[i]) == i, f'ERROR writing to {dut.reg_arr[i].name} != {i}'
+    sim(dut, proc)
         
-        # test writeback with writeback enabled
+# test writeback with writeback enabled
+def test_reg_writeback_en():
+    dut = Reg()
+    def proc():
         for i in range(16):
-            yield from init()
+            yield from _init(dut)
             yield dut.wr_en.eq(1)
             yield dut.rd_addr.eq(i)
             yield dut.rd.eq(i - 1)
@@ -214,10 +211,41 @@ def test_reg(filename="reg.vcd"):
             elif i == dut.ip.idx:
                 # ip should be incremented and not written to
                 assert (yield dut.reg_arr[i]) == i+1, f'ERROR {dut.ip.name} != {i + 1} should not be able to be directly written to'
+    sim(dut, proc)
 
-        yield dut.wr_en.eq(0)
+# check to make sure alu is writing values
+def test_reg_flg_write_aluflg():
+    dut = Reg()
+    def proc():
+        yield dut.flg.eq(0)
+        yield dut.alu_flgs.eq(Repl(1, dut.alu_flgs.width))
+        yield dut.wr_en.eq(1)
+        yield dut.flg.user_mode.eq(0)
+        yield dut.rd_addr.eq(dut.zx.idx)    # can be anything except flg register
+        yield dut.rd.eq(0xFFFF0000)         # this does not matter
+        yield from step()
+        assert (yield dut.flg) == (yield dut.alu_flgs), f'ERROR: alu is not writing to flg register'
+    sim(dut, proc)
 
-        # test flag register security
+def test_reg_flg_overwrite():
+    dut = Reg()
+    def proc():
+        yield dut.flg.eq(0)
+        yield dut.alu_flgs.eq(Repl(1, dut.alu_flgs.width))
+        yield dut.wr_en.eq(1)
+        yield dut.flg.user_mode.eq(0)
+        yield dut.flg[15].eq(1)
+        yield dut.flg[31].eq(1)
+        yield dut.rd_addr.eq(dut.flg.idx)
+        yield dut.rd.eq(0xFFFF0000)
+        yield from step()
+        assert (yield dut.flg) == (0xFFFF0000), f'ERROR: alu status should not be to flag'
+    sim(dut, proc)
+
+# test flag register security
+def test_reg_flg_read_usermode():
+    dut = Reg()
+    def proc():
         yield dut.flg.eq(0)
         yield dut.flg.user_mode.eq(1)
         yield dut.flg[15].eq(1)
@@ -225,8 +253,12 @@ def test_reg(filename="reg.vcd"):
         yield dut.rs1_addr.eq(dut.flg.idx)
         yield Settle()
         assert (yield dut.rs1) == 0x00008000, f'ERROR: able to read upper 16 bits of flg reg in user mode'
+    sim(dut, proc)
 
-        # test flag register security
+# test flag register security
+def test_reg_flg_write_usermode():
+    dut = Reg()
+    def proc():
         yield dut.flg.eq(0)
         yield dut.wr_en.eq(1)
         yield dut.flg.user_mode.eq(1)
@@ -236,7 +268,11 @@ def test_reg(filename="reg.vcd"):
         yield dut.rd.eq(0xABCD5789)
         yield from step()
         assert (yield dut.flg) == (0x80020000 | 0x5789), f'ERROR: able to write to upper 16 bits of flg reg in user mode'
+    sim(dut, proc)
 
+def test_reg_flg_read_systemmode():
+    dut = Reg()
+    def proc():
         yield dut.flg.eq(0)
         yield dut.flg.user_mode.eq(0)
         yield dut.flg[15].eq(1)
@@ -244,7 +280,12 @@ def test_reg(filename="reg.vcd"):
         yield dut.rs1_addr.eq(dut.flg.idx)
         yield Settle()
         assert (yield dut.rs1) == 0x80008000, f'ERROR: able to read all bits of flg reg in system mode'
+    sim(dut, proc)
 
+# make sure not to write alu flags when directly writing to flg register
+def test_reg_flg_write_systemmode():
+    dut = Reg()
+    def proc():
         yield dut.flg.eq(0)
         yield dut.wr_en.eq(1)
         yield dut.flg.user_mode.eq(0)
@@ -254,36 +295,10 @@ def test_reg(filename="reg.vcd"):
         yield dut.rd.eq(0xABCD5789)
         yield from step()
         assert (yield dut.flg) == (0xABCD5789), f'ERROR: unamble to write to all bits in supervisor mode'
+    sim(dut, proc)
 
-        # make sure not to write alu flags when directly writing to flg register
-        yield dut.flg.eq(0)
-        yield dut.alu_flgs.eq(Repl(1, dut.alu_flgs.width))
-        yield dut.wr_en.eq(1)
-        yield dut.flg.user_mode.eq(0)
-        yield dut.flg[15].eq(1)
-        yield dut.flg[31].eq(1)
-        yield dut.rd_addr.eq(dut.flg.idx)
-        yield dut.rd.eq(0xFFFF0000)
-        yield from step()
-        assert (yield dut.flg) == (0xFFFF0000), f'ERROR: alu status should not be to flag'
-
-        # check to make sure alu is writing values
-        yield dut.flg.eq(0)
-        yield dut.alu_flgs.eq(Repl(1, dut.alu_flgs.width))
-        yield dut.wr_en.eq(1)
-        yield dut.flg.user_mode.eq(0)
-        yield dut.rd_addr.eq(dut.zx.idx)    # can be anything except flg register
-        yield dut.rd.eq(0xFFFF0000)         # this does not matter
-        yield from step()
-        assert (yield dut.flg) == (yield dut.alu_flgs), f'ERROR: alu is not writing to flg register'
 
-    sim = Simulator(dut)
-    sim.add_clock(1e-6)
-    sim.add_sync_process(proc1)
-    
-    with sim.write_vcd(filename):
-        sim.run()
 
 if __name__ == '__main__':
-    reg = Reg()
-    cmd(reg, test_reg)
\ No newline at end of file
+    reg = InOutBuff(Reg())
+    cmd(reg)
\ No newline at end of file
diff --git a/hdl/lib/in_out_buff.py b/hdl/lib/in_out_buff.py
new file mode 100644
index 0000000..306f909
--- /dev/null
+++ b/hdl/lib/in_out_buff.py
@@ -0,0 +1,28 @@
+from amaranth import *
+
+class InOutBuff(Elaboratable):
+    '''
+    This module wraps another modules input and output with a buffer
+    This is usefull for doing timeing analysis on combinational logic 
+
+    An instance of a module should be passed, not the module itself
+    '''
+    def __init__(self, sub_module: Elaboratable):
+        assert sub_module.ports is not None, 'sub_module must have ports'
+
+        self.sub_module = sub_module
+        ports_in = [Signal(port.width, name=port.name + '_inbuf') for port in sub_module.ports['in']]
+        ports_out = [Signal(port.width, name=port.name + '_outbuf') for port in sub_module.ports['out']]
+        self.ports = {'in': ports_in, 'out': ports_out}
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.sub = self.sub_module
+
+        for i in range(len(self.ports['in'])):
+            m.d.sync += self.sub_module.ports['in'][i].eq(self.ports['in'][i])
+
+        for i in range(len(self.ports['out'])):
+            m.d.sync += self.ports['out'][i].eq(self.sub_module.ports['out'][i])
+
+        return m
\ No newline at end of file