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AgeCommit message (Expand)Author
2022-09-06consolidated aluflagsjjsuperpower
2022-09-06updated templatejjsuperpower
2022-09-05fixed tb for shiftregjjsuperpower
2022-09-05honestly i don't know what I didjjsuperpower
2022-09-05moveing file aroundjjsuperpower
2022-09-05updated testbench formatjjsuperpower
2022-09-05Restructuring and organizingjjsuperpower
2022-08-30reorganized hdljjsuperpower
2022-08-29fixed parity checkjjsuperpower
2022-08-27register partially testedjjsuperpower
2022-08-27moved interupt control outside regjjsuperpower
2022-08-27coded but not tested Register filejjsuperpower
2022-08-24added odd flag bitjjsuperpower
2022-08-24Update ALU, added more opsjjsuperpower
2022-08-23Update the ISA specificationsDanny Holman
2022-08-21minor changejjsuperpower
2022-08-21basic alu coded and testedjjsuperpower
2022-08-15updated ISAjjsuperpower
2022-08-15added templatejjsuperpower
2022-08-10added make filejjsuperpower
2022-08-07basic shift register workingjjsuperpower
2022-08-04Updated .gitignorejjsuperpower
2022-08-04deprecated all myhdl stuff, moving to Amaranthjjsuperpower
2022-08-02Uploading to remotejjsuperpower
2022-06-29fixed shift_reg for exportjjsuperpower
2022-06-28vcd file working for cosimjjsuperpower
2022-06-28added template, ResetSyncjjsuperpower
2022-06-26added templatejjsuperpower
2022-06-26restructured folderjjsuperpower
2022-06-26shift_reg donejjsuperpower
2022-06-24before myhdl_wraperjjsuperpower
2022-06-24combine shiftreg workingjjsuperpower
2022-06-24testing multilevel convertjjsuperpower
2022-06-23update gitignorejjsuperpower
2022-06-23basic myhdl setup workingjjsuperpower
2022-06-19added hdl folderjjsuperpower