diff options
author | jjsuperpower <jjs29356@gmail.com> | 2022-06-26 11:11:43 -0500 |
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committer | jjsuperpower <jjs29356@gmail.com> | 2022-06-26 11:11:43 -0500 |
commit | 5de4d07c6db81a9ed21cd39aaef229fb94c4bb6b (patch) | |
tree | a73138c38bd71079ffcebc73fe67a1545c6d4fa4 | |
parent | 987134966d0c3ab9b1a5775c8f01fa707408780b (diff) |
added template
-rw-r--r-- | hdl_lab/Makefile | 2 | ||||
-rw-r--r-- | hdl_lab/hdl/constants.py | 5 | ||||
-rw-r--r-- | hdl_lab/hdl/myhdl_wrap.py | 31 | ||||
-rw-r--r-- | hdl_lab/hdl/shift_reg.py | 1 | ||||
-rw-r--r-- | hdl_lab/hdl/template.py | 67 |
5 files changed, 104 insertions, 2 deletions
diff --git a/hdl_lab/Makefile b/hdl_lab/Makefile index c40b1cf..a85bbd8 100644 --- a/hdl_lab/Makefile +++ b/hdl_lab/Makefile @@ -10,4 +10,4 @@ test-w: py.test -v $(HDL) clean: - $(RM) -rf simulation/* gen_verilog/* __pycache__/* .pytest_cache/*
\ No newline at end of file + $(RM) -rf simulation/* gen_verilog/* hdl/__pycache__/* .pytest_cache/*
\ No newline at end of file diff --git a/hdl_lab/hdl/constants.py b/hdl_lab/hdl/constants.py new file mode 100644 index 0000000..d40d7c1 --- /dev/null +++ b/hdl_lab/hdl/constants.py @@ -0,0 +1,5 @@ +SIM_DIR = './simulation/' +GEN_VERILOG = './gen_verilog/' + +IVERILOG = 'iverilog ' +VVP = 'vvp -M ./ -m myhdl '
\ No newline at end of file diff --git a/hdl_lab/hdl/myhdl_wrap.py b/hdl_lab/hdl/myhdl_wrap.py new file mode 100644 index 0000000..2e8fe4e --- /dev/null +++ b/hdl_lab/hdl/myhdl_wrap.py @@ -0,0 +1,31 @@ +import os +from myhdl import * +from constants import * + +class Myhdl_Wrapper(): + def __init__(self): + self.class_name = self.__class__.__name__ + + def _export(self, **kargs): + inst = getattr(self, self.class_name)(**kargs) + inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}") + + + + # This function links myhdl to icarus verilog sim + def _cosim(self, **kargs): #these should have the same signals as logic(), + + iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v" + vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o" + + os.system(iverilog_cmd) + return Cosimulation(vvp_cmd, **kargs) + + def sim(self): + tb = self.tb(getattr(self, self.class_name)) + tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim") + tb.run_sim() + + def cosim(self): + tb = self.tb(self._cosim) + tb.run_sim()
\ No newline at end of file diff --git a/hdl_lab/hdl/shift_reg.py b/hdl_lab/hdl/shift_reg.py index 28914f1..d463a9f 100644 --- a/hdl_lab/hdl/shift_reg.py +++ b/hdl_lab/hdl/shift_reg.py @@ -1,4 +1,3 @@ -from turtle import width from myhdl import * from myhdl_wrap import Myhdl_Wrapper diff --git a/hdl_lab/hdl/template.py b/hdl_lab/hdl/template.py new file mode 100644 index 0000000..09a6f7f --- /dev/null +++ b/hdl_lab/hdl/template.py @@ -0,0 +1,67 @@ +from typing import Callable +from myhdl import * +from myhdl_wrap import Myhdl_Wrapper + +import random +from random import randint + +random.seed(63) + +class Template(Myhdl_Wrapper): + def __init__(self): + super().__init__() + + # Main code, this is the actual logic + @staticmethod + @block + def Template(args): # this must be the same name as the class name + + @instance + def logic(): + ... + + return logic + + + @block + def tb(self, func: Callable): + reset = Signal(False) + clk = Signal(bool(0)) + ... + + dut = func(..., clk=clk, reset=reset) + + @always(delay(...)) + def clock_gen(): + clk.next = not clk + + @instance + def monitor(): + ... + + @instance + def stimulus(): + ... + + raise StopSimulation + + + return dut, clock_gen, monitor, stimulus + + def export(self): + reset = Signal(False) + clk = Signal(bool(0)) + ... + + # assigning signals, kargs only + self._export(..., clk=clk, reset=reset) + + +def test_template_sim(): + hdl = Template() + hdl.sim() + +def test_template_cosim(): + hdl = Template() + hdl.export() + hdl.cosim() |