diff options
| author | jjsuperpower <jjs29356@gmail.com> | 2022-06-19 22:20:25 -0500 |
|---|---|---|
| committer | jjsuperpower <jjs29356@gmail.com> | 2022-06-19 22:20:25 -0500 |
| commit | 26169bec7ae7b85d938f5d3c6e969885f2230541 (patch) | |
| tree | 86752721345fc913acc1d3f8f9e4fdd322c97ae9 | |
added hdl folder
| -rw-r--r-- | .gitignore | 1 | ||||
| -rw-r--r-- | Makefile | 24 | ||||
| -rw-r--r-- | doc/DJ-ISA_rev_0.0.3.md | 174 | ||||
| -rw-r--r-- | doc/LICENSE | 451 | ||||
| -rw-r--r-- | doc/Makefile | 24 | ||||
| -rw-r--r-- | doc/README.md | 8 | ||||
| -rw-r--r-- | doc/missfont.log | 3 | ||||
| -rw-r--r-- | doc/src/01-About.md | 73 | ||||
| -rw-r--r-- | doc/src/02-Instruction-Format.md | 5 | ||||
| -rw-r--r-- | doc/src/03-Instruction-Set-Reference.md | 92 | ||||
| -rw-r--r-- | doc/src/04-System-Architecture-Overview.md | 14 | ||||
| -rw-r--r-- | doc/src/05-Interrupt-Handling.md | 30 | ||||
| -rw-r--r-- | doc/src/06-Memory-Management.md | 11 | ||||
| -rw-r--r-- | doc/src/figs/registers.svg | 4 | ||||
| -rw-r--r-- | doc/src/title.txt | 8 | ||||
| -rw-r--r-- | hdl/testing/.gitignore | 1 | ||||
| -rw-r--r-- | hdl/testing/hello_world.py | 129 | ||||
| -rw-r--r-- | hdl/testing/inc.v | 39 | ||||
| -rw-r--r-- | hdl/testing/shift_reg.py | 0 | ||||
| -rw-r--r-- | hdl/testing/tb_inc.v | 26 |
20 files changed, 1117 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..a136337 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +*.pdf diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..98545df --- /dev/null +++ b/Makefile @@ -0,0 +1,24 @@ +BOOK:=manual.pdf +SOURCES:=src/*.md +FIGURES:=$(shell find . -name "*.svg") +PFLAGS:=--table-of-contents \ + --pdf-engine=xelatex \ + --from=markdown \ + --number-sections \ + --indented-code-classes=javascript \ + --highlight-style=monochrome \ + -V mainfont="Apple Garamond" \ + -V monofont="FreeMono" \ + -V documentclass=report \ + -V papersize=letter \ + -V geometry:margin=1in + +.PHONY: all clean + +all: $(BOOK) + +$(BOOK): $(SOURCES) src/title.txt $(FIGURES) + pandoc $^ -o $@ $(PFLAGS) + +clean: + $(RM) *.pdf diff --git a/doc/DJ-ISA_rev_0.0.3.md b/doc/DJ-ISA_rev_0.0.3.md new file mode 100644 index 0000000..f8c85a3 --- /dev/null +++ b/doc/DJ-ISA_rev_0.0.3.md @@ -0,0 +1,174 @@ +# Vertex KISS 48 - Machine Code Spec + +## General Instruction Format + X = HEX + B = BIN + + d = HEX (not used / don't care) + + MAX INSTRUCTIIONS = 256 + ALL INSTRUCTIONS ARE ATOMIC + +### C-Type, Control + XX XX XX XXXXXX + Opcode dd RS1 Address/IMM + +### I-Type, Immediate + XX XX XX XXXXXX + Opcode RD RS IMM + +### R-Type, Arithmetic + XX XXXX XX XX XX + Opcode dddd RD RS1 RS2 + +### J-Type, Jump / Branch + XX XX XXXX XXXX + Opcode dd Address (XX * 2^32 + XXXX) + +## Registers + Maximum registers = 16 + Register width = 32 + All are R/W except 0X + + 0X Always Zero + AX GP-0 + BX GP-1 + CX GP-2 + DX GP-3 + EX GP-4 + FX GP-5 + GX GP-6 + FX GP-7 + HI Mult/Div Hi + LO Mult/Div Lo + FLG Processor Flags + CRX Control register (Writable only in supervisor mode) + IP Instruction Pointer + SP Stack Pointer + + +### FLG Register Bitfield + These registers are Read/Write + + NOTE: + I think this is needed in order to restore from interupt, if this is not true, then I propose the + bottom half be read only and the top half be read / write. Then just re-assign the registers to differnt locations + + FLG[0] Carry + FLG[1] Overflow + FLG[2] Zero + FLG[3] Sign + FLG[4]* Interrupt Enable + FLG[5]* User Mode + FLG[6-31] RESERVED + +*To be moved to control register* + +## Integer Instructions + +### R-Type + ADD RD, RS1, RS2 RD = RS1 + RS2 + SUB RD, RS1, RS2 RD = RS1 - RS2 + XOR RD, RS1, RS2 RD = RS1 ^ RS2 + OR RD, RS1, RS2 RD = RS1 | RS2 + AND RD, RS1, RS2 RD = RS1 & RS2 + LSL RD, RS1, RS2 RD = RS1 << RS2 (logical) + LSR RD, RS1, RS2 RD = RS1 >> RS2 (logical) + ASR RD, RS1, RS2 RD = RS1 >> RS2 + MUL RD, RS1, RS2 HI,LO = RS1 * RS2 + MULU RD, RS1, RS2 HI,LO = RS1 * RS2 + DIV RD, RS1, RS2 HI,LO = RS1 / RS2 + DIVU RD, RS1, RS2 HI,LO = RS1 / RS2 (unsigned) + + LDB RD, RS1, RS2 RD = &(RS1 + RS2) Load Byte + STB RD, RS1, RS2 &(RS1 + RS2) = (RD >> 24) Store Byte + LDW RD, RS1, RS2 RD = &(RS1 + RS2) Load Word (4 bytes) + STW RD, RS1, RS2 &(RS1 + RS2) = RD Store Word (4 bytes) + + +### I-Type + ADDI RD, RS, IMM RD = RS + IMM + SUBI RD, RS, IMM RD = RS - IMM + XORI RD, RS, IMM RD = RS ^ IMM + ORI RD, RS, IMM RD = RS | IMM + ANDI RD, RS, IMM RD = RS & IMM + LSLI RD, RS, IMM RD = RS << IMM (logical) + LSRI RD, RS, IMM RD = RS >> IMM (logical) + ASRI RD, RS, IMM RD = RS >> IMM + MULI dd, RS, IMM HI,LO = RS * IMM + MULIU dd, RS, IMM HI,LO = RS * IMM + DIVI dd, RS, IMM HI,LO = RS / IMM + DIVIU dd, RS, IMM HI,LO = RS / IMM (unsigned) + + LDBI RD, RS, RS2 RD = &(RS + IMM) Load Byte + STBI RD, RS, RS2 &(RS + IMM) = (RD >> 24) Store Byte + LDWI RD, RS, RS2 RD = &(RS + IMM) Load Word (4 bytes) + STWI RD, RS, RS2 &(RS + IMM) = RD Store Word (4 bytes) + + +### Jump Instructions + JMP ADDR IP = ADDR + JEQ ADDR if (FLG.ZERO == 1) IP = ADDR + JLT ADDR if (FLG.SIGN == 0) IP = ADDR + JGT* ADDR if (FLG.SIGN == 1) IP = ADDR + JLE ADDR if (FLG.ZERO == 1 & FLG.SIGN == 0) IP = ADDR + JGE ADDR if (FLG.ZERO == 1 & FLG.SIGN == 1) IP = ADDR + JLTU ADDR if (FLG.OVERFLOW == 1) IP = ADDR + JGTU ADDR if (FLG.OVERFLOW == 0) IP = ADDR + JLEU* ADDR if (FLG.ZERO == 1 & FLG.SIGN == 0) IP = ADDR + JGEU* ADDR if (FLG.ZERO == 1 & FLG.SIGN == 1) IP = ADDR + +*Duplicate OP code* + +### Control Instructions + NOP Do nothing -> opcode = ZERO + PUSHR RS SP+=4;SP = RS + POPR RS RS = SP;SP-=4 + PUSHI IMM SP+=4;SP = IMM + INVP IMM Invalidate entry in TLB + RET POPR BX;JMP BX + CALL IMM PUSHI $;JMP ADDR + INT IMM PUSHR SP;PUSHR FLG;PUSHR IP;PUSHI errno;IP = IDT[IMM] + IRET POPR IP;POPR FLG;POPR SP + SIF Set interrupt flag + CIF Clear interrupt flag + +## Interrupt Descriptor Table +This will be in a fixed memory location, this will contain pointers to the interupt function. Once an interupt is entered, all interupts are turned off. + + IDT[0] Divide-by-zero exception + IDT[1] Hardware error (NMI) + IDT[2] Overflow + IDT[3] Invalid Opcode + IDT[4] General-protection fault + IDT[5] Page fault + IDT[6-15] RESERVED + + IDT[16-255] Platform interrupts (PIC, hard drive, keyboard, etc.) + IDT[80] Software interrupt (reserved for OS) + + + + + + + + + + +## Page Directory + +The page directory contains 1024 page tables that have 1024 entries. + +### Page table layout + +PT[0] Present +PT[1] R/W +PT[2] User-mode +PT[3-4] RESERVED +PT[5] Accessed +PT[6-7] RESERVED +PT[8-31] Physical address of page table (XX * 2^16 + XXXX) + + *This is still WIP but I wanted to get your input on the layout. I also have + the jank memory offset that will more than likely change.* diff --git a/doc/LICENSE b/doc/LICENSE new file mode 100644 index 0000000..857214d --- /dev/null +++ b/doc/LICENSE @@ -0,0 +1,451 @@ + + GNU Free Documentation License + Version 1.3, 3 November 2008 + + + Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. + <https://fsf.org/> + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + +0. 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This work is licensed under the terms of the GNU Free Documentation +License v1.3. + +Copyright (C) 2022 Danny Holman <dholman@gymli.org> + Jon Sanderson <jjsuperpower@gmail.com> diff --git a/doc/missfont.log b/doc/missfont.log new file mode 100644 index 0000000..7e582e9 --- /dev/null +++ b/doc/missfont.log @@ -0,0 +1,3 @@ +mktextfm FreeMono +mktextfm FreeMono +mktextfm FreeMono diff --git a/doc/src/01-About.md b/doc/src/01-About.md new file mode 100644 index 0000000..0468708 --- /dev/null +++ b/doc/src/01-About.md @@ -0,0 +1,73 @@ +# About this Manual + +This manual describes the architecture and programming environment of a Vertex +Mark I microprocessor. This manual applies to application programmers, operating +system programmers and BIOS designers. + +## Notational Conventions + +This manual uses specific notation for data-structure formats, for symbolic +representation and for hexadecimal and binary numbers. A review of this notation +makes the manual easier to read. + +### Bit and Byte Order + +In illustrations of data structures in memory, smaller addresses appear toward +the bottom of the figure; addresses increase toward the top. Bit positions are +numbered from right to left. The numerical value of a set bit is two raised to +the power of the bit position. Vertex processors are "little endian" machines; +this means the bytes of a word are numbered starting from the least significant +byte. Figure 1.1 illustrates these conventions. + +### Reserved Bits + +In many register and memory layout descriptions, certain bits are marked as +**reserved**. When bits are marked as reserved, it is essential for +compatibility with future processors that software treat these bits as having +a future, but unknown, use. These bits should be treated as, not only undefined, +but unpredictable. + +### Instruction Operands + +When instructions are represented symbolically, a subset of the Vertex-32 +assembly language is used. In this subset, an instruction has the following +format: + +``` +label: mnemonic argument1, argument2, argument3 +``` + +where: + +* A **label** is an identifier which is followed by a colon +* A **mnemonic** is a reserved name for an instruction opcode +* The operands *argument1*, *argument2* and *argument3* are optional. There may + be from zero to three operands, depending on the opcode. + +When three operands are present in an arithmetic or logical operation, the first +operand is the destination register and the remaining two are either source +registers or immediate values. For example: + +``` +load: ADDI AX, BX, subtotal +``` + +In this example, `ADDI` is the mnemonic identifier of an opcode, `AX` is the +destination operand, and `BX` and `subtotal` are the source operands. + +### Hexadecimal and Binary Numbers + +Base 16 (hexadecimal) numbers are represented by a '0x' followed by a string of +hexadecimal digits. A hexadecimal digit is a character from '0' to '9' and 'A' +to 'F'. Base 2 (binary) numbers are represented by a string of 1s and 0s, +sometimes preceded by '0b' (for example, 0b1010). The '0b' designation is only +used in situations in which confusion about a number's base may arise. + +### Exceptions + +An exception is an event that typically occurs when an instruction causes an +error. For example, an attempt to divide by zero generates a divide-by-zero +exception. All exceptions provide either an error code or 0, indicating no +error. An error code reports additional information about the error. For +example, a page fault would provide a fault code indicating what caused the page +fault. diff --git a/doc/src/02-Instruction-Format.md b/doc/src/02-Instruction-Format.md new file mode 100644 index 0000000..e08f110 --- /dev/null +++ b/doc/src/02-Instruction-Format.md @@ -0,0 +1,5 @@ +# Instruction Format + +## Instruction Format for V32 Mode + +WIP diff --git a/doc/src/03-Instruction-Set-Reference.md b/doc/src/03-Instruction-Set-Reference.md new file mode 100644 index 0000000..e258393 --- /dev/null +++ b/doc/src/03-Instruction-Set-Reference.md @@ -0,0 +1,92 @@ +# Instruction Set Reference + +This chapter describes the instruction set for the Vertex-32 and Vertex-64 +architectures in V32 and V64 modes of operation. For each instruction, each +operand combination is described, a description of the effect upon the FLG +register and a summary of possible exceptions are also provided. + +## Registers + +Figure 3.1 shows the initial state of the registers in the ISA. For V32, the +16 registers are each 32 bits wide. Register `0X` is hardwired with all bits +equal to 0. General purpose registers `AX` to `GX` hold values that various +instructions interpret as a collection of Boolean values, or as two's +complement signed binary integers or unsigned binary integers. The registers +`PTR`, `IDTR` and `CRX` are considered privileged and writing to them in the +unprivileged state will generate a general protection fault. + +## Base Instruction Formats + +In the core V32 ISA, there are four instruction formats (C/I/R/J), as shown in +Figure 3.3. All are a fixed 32 bits in length and must be aligned on a four-byte +boundary in memory. An instruction alignment exception is generated if a branch +or jump instruction is called on an address that is not four-byte aligned. No +exception is generated on a branch or jump not taken. + +## Integer Instructions + +Most integer computational instructions operate on 32 or 64 bit values held in +a register or memory location. Integer instructions are encoded as +register-immediate operations using the I-type format or as register-register +operations using the R-type format. The destination is `RD` for both +register-immediate and register-register operations. If any of the following +instructions cause an overflow or underflow, the overflow flag is set. + +### Integer-Register Instructions + +The instructions that follow are operations between registers; an attempt to use +a non-register operand will result in an invalid opcode exception. The format +for these exceptions follow Figure 3.4. + +#### ADD + +`ADD` adds the second and third operands and stores the result in the first +operand. + +#### SUB + +`SUB` subtracts the third operand from the second operand and stores the result +in the first operand. + +#### MUL/MULU + +`MUL` multiplies the second operand by the third operand and stores the result +in the first operand. `MULU` performs the same operation on unsigned integers. + +#### DIV/DIVU + +`DIV` divides the second operand by the third operand. The dividend is stored in +the upper 16 bits of the first operand, and the remainder is stored in the lower +16 bits. `DIVU` performs the same operation on unsigned integers. + +#### XOR + +`XOR` performs a bitwise 'exclusive or' operation between the second and third +operands and stores the result in the first operand. + +#### OR + +`OR` performs a bitwise 'or' operation between the second and third operands and +stores the result in the first operand. + +#### AND + +`AND` performs a bitwise 'and' operation between the second and third operands +and stores the result in the first operand. + +#### LSL + +`LSL` performs a logical shift left. The second operand is shifted left by `n` +bits, where `n` is the third operand. The result is stored in the first operand. + +#### LSR + +`LSR` performs a logical shift right. The second operand is shifted right by +'n' bits, where 'n' is the third operand. The result is stored in the first +operand. + +#### ASR + +`ASR` performs an arithmetic shift right. The second operand is shifted right by +'n' bits, where 'n' is the third operand. The result is stored in the first +operand. diff --git a/doc/src/04-System-Architecture-Overview.md b/doc/src/04-System-Architecture-Overview.md new file mode 100644 index 0000000..2aa76d3 --- /dev/null +++ b/doc/src/04-System-Architecture-Overview.md @@ -0,0 +1,14 @@ +# System Architecture Overview + +## Overview of the System-level Architecture + +The system-level architecture consists of a set of registers, data structures +and instructions designed to support basic system management operations such as +memory management, interrupt handling, task management and control of multiple +processors. Figure 4.1 describes the registers and data structures relevant to +V32 mode. + +## Memory Management Overview + +The Vertex-32 architecture provides several instructions that create and +manipulate pages and page tables. diff --git a/doc/src/05-Interrupt-Handling.md b/doc/src/05-Interrupt-Handling.md new file mode 100644 index 0000000..0c549e1 --- /dev/null +++ b/doc/src/05-Interrupt-Handling.md @@ -0,0 +1,30 @@ +# Interrupt and Exception Handling + +This chapter describes the interrupt and exception-handling mechanism on a +Vertex-32 or Vertex-64 processor. + +## Interrupts Overview + +Interrupts and exceptions are events that get triggered either upon a special +condition or when the instruction `INT interrupt_number` is executed. Typically, +an interrupt forces a transfer of execution from the currently executing task to +a special routine called an interrupt handler or an exception handler. The +action taken by a processor in response to an interrupt is referred to as +servicing or handling the interrupt or exception. + +Interrupts can occur at regular intervals or randomly during the execution of a +task or software routine in response to signals from hardware, such as requests +from peripheral devices. Interrupts can also be generated by software by calling +the `INT` instruction. + +Exceptions occur when the processor detects an error condition while executing +an instruction. For instance, the processor could detect that a program is +requesting a page that is currently not mapped, generating a page fault. + +When an interrupt is received, the currently running task is suspended while the +processor services the interrupt or exception. Upon completion of the interrupt +handler, execution is returned to the suspended task without loss of continuity. +If the exception cannot be handled or the exception handler does not return, a +double fault is generated. If a further exception is encountered while servicing +the double fault, it is considered an unrecoverable error and the processor is +reset. diff --git a/doc/src/06-Memory-Management.md b/doc/src/06-Memory-Management.md new file mode 100644 index 0000000..0813c6a --- /dev/null +++ b/doc/src/06-Memory-Management.md @@ -0,0 +1,11 @@ +# Memory Management + +This chapter describes the Vertex-32 and Vertex-64 architecture's memory +management facilities, including physical memory requirements and paging. + +## Memory Management Overview + +The Vertex family of processors provide facilities to perform demand-paged +paging algorithms. Although recommended for most applications, the paging +mechanism can be disabled and memory can then be access directly. Segmentation, +such as what is found on Intel's x86 architecture, is not supported. diff --git a/doc/src/figs/registers.svg b/doc/src/figs/registers.svg new file mode 100644 index 0000000..1522f2a --- /dev/null +++ b/doc/src/figs/registers.svg @@ -0,0 +1,4 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Do not edit this file with editors other than diagrams.net --> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd"> +<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" version="1.1" width="141px" height="451px" viewBox="-0.5 -0.5 141 451" content="<mxfile host="Electron" modified="2022-05-06T03:17:17.485Z" agent="5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) draw.io/17.4.2 Chrome/100.0.4896.60 Electron/18.0.1 Safari/537.36" etag="LDFEIayXnVHNOMXlRYny" version="17.4.2" type="device"><diagram id="aj0NjsLKcaomzQoa0Eas" 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\ No newline at end of file diff --git a/doc/src/title.txt b/doc/src/title.txt new file mode 100644 index 0000000..8ff72f6 --- /dev/null +++ b/doc/src/title.txt @@ -0,0 +1,8 @@ +--- +title: Vertex Architecture Manual +subtitle: A KISS Architecture +author: + - Danny Holman + - Jon Sanderson +date: June 14, 2022 +--- diff --git a/hdl/testing/.gitignore b/hdl/testing/.gitignore new file mode 100644 index 0000000..be78124 --- /dev/null +++ b/hdl/testing/.gitignore @@ -0,0 +1 @@ +quartus
\ No newline at end of file diff --git a/hdl/testing/hello_world.py b/hdl/testing/hello_world.py new file mode 100644 index 0000000..2167856 --- /dev/null +++ b/hdl/testing/hello_world.py @@ -0,0 +1,129 @@ +# from myhdl import block, delay, always, now + +# @block +# def HelloWorld(): + +# @always(delay(10)) +# def say_hello(): +# print("%s Hello World!" % now()) + +# return say_hello + + +# inst = HelloWorld() +# inst.run_sim(30) + +######################################################## + +# from myhdl import block, Signal, delay, always, now + +# @block +# def HelloWorld(): + +# clk = Signal(0) + +# @always(delay(10)) +# def drive_clk(): +# clk.next = not clk + +# @always(clk.posedge) +# def say_hello(): +# print("%s Hello World!" % now()) + +# return drive_clk, say_hello + + +# inst = HelloWorld() +# inst.run_sim(50) + +######################################################## + +# from myhdl import block, always_comb, Signal + +# @block +# def mux(z, a, b, sel): + +# """ Multiplexer. + +# z -- mux output +# a, b -- data inputs +# sel -- control input: select a if asserted, otherwise b + +# """ + +# @always_comb +# def comb(): +# if sel == 1: +# z.next = a +# else: +# z.next = b + +# return comb + +# import random +# from myhdl import block, instance, Signal, intbv, delay + +# random.seed(5) +# randrange = random.randrange + +# @block +# def test_mux(): + +# z, a, b, sel = [Signal(intbv(0)) for i in range(4)] + +# mux_1 = mux(z, a, b, sel) + +# @instance +# def stimulus(): +# print("z a b sel") +# for i in range(12): +# a.next, b.next, sel.next = randrange(8), randrange(8), randrange(2) +# yield delay(10) +# print("%s %s %s %s" % (z, a, b, sel)) + +# return mux_1, stimulus + +# tb = test_mux() +# tb.run_sim() + + +######################################################## + +from myhdl import block, always_seq + +@block +def inc(count, enable, clock, reset): + """ Incrementer with enable. + + count -- output + enable -- control input, increment when 1 + clock -- clock input + reset -- asynchronous reset input + """ + + @always_seq(clock.posedge, reset=reset) + def seq(): + if enable: + count.next = count + 1 + + return seq + +from myhdl import Signal, ResetSignal, modbv + +def convert_inc(hdl): + """Convert inc block to Verilog or VHDL.""" + + m = 8 + + count = Signal(modbv(0)[m:]) + enable = Signal(bool(0)) + clock = Signal(bool(0)) + reset = ResetSignal(0, active=0, isasync=True) + + inc_1 = inc(count, enable, clock, reset) + + inc_1.convert(hdl=hdl) + + +convert_inc(hdl='Verilog') +convert_inc(hdl='VHDL')
\ No newline at end of file diff --git a/hdl/testing/inc.v b/hdl/testing/inc.v new file mode 100644 index 0000000..2f3291b --- /dev/null +++ b/hdl/testing/inc.v @@ -0,0 +1,39 @@ +// File: inc.v +// Generated by MyHDL 0.11 +// Date: Sun Jun 19 22:02:52 2022 + + +`timescale 1ns/10ps + +module inc ( + count, + enable, + clock, + reset +); +// Incrementer with enable. +// +// count -- output +// enable -- control input, increment when 1 +// clock -- clock input +// reset -- asynchronous reset input + +output [7:0] count; +reg [7:0] count; +input enable; +input clock; +input reset; + + +always @(posedge clock, negedge reset) begin: INC_SEQ + if (reset == 0) begin + count <= 0; + end + else begin + if (enable) begin + count <= (count + 1); + end + end +end + +endmodule diff --git a/hdl/testing/shift_reg.py b/hdl/testing/shift_reg.py new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/hdl/testing/shift_reg.py diff --git a/hdl/testing/tb_inc.v b/hdl/testing/tb_inc.v new file mode 100644 index 0000000..c0cf480 --- /dev/null +++ b/hdl/testing/tb_inc.v @@ -0,0 +1,26 @@ +module tb_inc; + +wire [7:0] count; +reg enable; +reg clock; +reg reset; + +initial begin + $from_myhdl( + enable, + clock, + reset + ); + $to_myhdl( + count + ); +end + +inc dut( + count, + enable, + clock, + reset +); + +endmodule |
