testing multilevel convert

1 files changed, 28 insertions, 0 deletions

diff --git a/hdl/testing/top.py b/hdl/testing/top.py
new file mode 100644
index 0000000..55c5714
--- /dev/null
+++ b/hdl/testing/top.py
@@ -0,0 +1,28 @@
+from myhdl import *
+from constants import GEN_VERILOG
+from shift_reg import ShiftReg
+
+logic = ShiftReg.logic
+
+
+@block
+def top(clk, reset, in0, out0):
+
+    n0 = Signal(modbv(0)[8:])
+    
+
+    sr0 = logic(clk=clk, reset=reset, in0=in0, out0=n0)
+    sr1 = logic(clk=clk, reset=reset, in0=n0[7], out0=out0)
+
+    return sr0, sr1
+
+def convert():
+        reset = ResetSignal(0, 0, True)
+        clk = Signal(bool(0))
+        in0 = Signal(bool(0))
+        out0 = Signal(modbv(0)[8:])
+
+        inst = top(reset=reset, clk=clk, in0=in0, out0=out0)
+        inst.convert(hdl='Verilog', path=GEN_VERILOG)
+
+convert()
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