updated ISA

3 files changed, 64 insertions, 17 deletions

diff --git a/doc/DJ-ISA_rev_0.0.4.md b/doc/DJ-ISA_rev_0.0.5.md
index 8c7266d..66f57a6 100644
--- a/doc/DJ-ISA_rev_0.0.4.md
+++ b/doc/DJ-ISA_rev_0.0.5.md
@@ -25,12 +25,12 @@ I propose a different name:
     Also I have been reading about caching, I think the instruction width needs to be the same as the data memory
 
 ### C-Type, Control
-    XX         X       XXXXX
-    Opcode     RS1     IMM
+    XX       X    X       XXXX
+    Opcode   d    RS1     IMM
 
 ### I-Type, Immediate
     XX        X     X     XXXX
-    Opcode    RD    RS    IMM
+    Opcode    RD    RS1   IMM
 
 ### R-Type, Arithmetic
     XX         X      X      X      XXX
@@ -60,27 +60,34 @@ I propose a different name:
     FX      GP-7
     HI      Mult/Div Hi
     LO      Mult/Div Lo
-    FLG     Processor Flags
-    CRX     Control register (Writable only in supervisor mode)
+    FG      Processor Flags
+    CR      Control register (Writable only in supervisor mode)
     IP      Instruction Pointer
     SP      Stack Pointer
-    JMP     Jump Address
+    JA      Jump Address
 
     ^ I have added this, it is part of my proposal for changing how jumps work
 
 
-### FLG Register Bitfield
+### FG Flag Register Bitfield
     These registers are Read/Write
+    They are automaticaly writen two by the processor
+
+    FG[0]           Carry
+    FG[1]           Overflow
+    FG[2]           Zero
+    FG[3]           Sign
+    FG[4-31]        RESERVED
+
+### CR Control Register Bitfield
+    These register are Read/Write in System mode, Read Only in User Mode
+
+    CR[0]           Interupt Enable
+    CR[1]           User Mode
+    CR[2]           DMA
+    CR[2-31]        RESERVED
 
-    FLG[0]          Carry
-    FLG[1]          Overflow
-    FLG[2]          Zero
-    FLG[3]          Sign
-    FLG[4]*         Interrupt Enable
-    FLG[5]*         User Mode
-    FLG[6-31]       RESERVED
 
-*To be moved to control register*
 
 ## Integer Instructions
 
@@ -169,7 +176,7 @@ I propose a different name:
     NOP                     Do nothing -> opcode = ZERO
     PUSHR   RS              SP+=1     ;*SP = RS
     POPR    RS              RS = *SP  ;SP-=1
-    PUSHA                   PUSHR AX, BX, CX, DX, EX, FX, GX, FX, HI, LO, FLG, CRX, IP, SP, JMP
+    PUSHA                   PUSHR AX, BX, CX, DX, EX, FX, GX, FX, HI, LO, FG, CR, IP, SP, JA
     POPA                    POP reverse PUSHR, SP not affected
     PUSHI   IMM             SP+=1     ;*SP = IMM
     INVP    IMM             Invalidate entry in TLB
diff --git a/hdl/core.py b/hdl/core.py
new file mode 100644
index 0000000..6ef02fb
--- /dev/null
+++ b/hdl/core.py
@@ -0,0 +1,40 @@
+from amaranth import *
+from amaranth.sim import Simulator, Settle, Delay
+
+from utils import cmd
+
+class Template(Elaboratable):
+    def __init__(self):
+        ...
+
+        self.ports = [...]
+
+    def elaborate(self, platform):
+        m = Module()
+
+        ...
+
+        return m
+
+
+
+        
+
+def test(filename="out.vcd"):
+    dut = ...
+
+    def proc1():
+        ...
+
+
+    sim = Simulator(dut)
+    sim.add_clock(1e-6)
+    sim.add_sync_process(proc1)
+    
+    with sim.write_vcd(filename):
+        sim.run()
+
+
+if __name__ == '__main__':
+    shift_reg = Template(...)
+    cmd(shift_reg, test)
\ No newline at end of file
diff --git a/hdl/template.py b/hdl/template.py
index 5df554c..64f0655 100644
--- a/hdl/template.py
+++ b/hdl/template.py
@@ -32,5 +32,5 @@ def test(filename="out.vcd"):
 
 
 if __name__ == '__main__':
-    shift_reg = Template(8)
+    shift_reg = Template(...)
     cmd(shift_reg, test)
\ No newline at end of file