| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-02-04 | allowing for control signals with differnet width | jjsuperpower | |
| 2023-01-24 | working on reading control lines from csv | jjsuperpower | |
| 2023-01-24 | fixed shift with number greater than 32 | jjsuperpower | |
| 2023-01-22 | moving machine codes to central file | jjsuperpower | |
| 2023-01-22 | misc | jjsuperpower | |
| 2023-01-22 | added rtlil export | jjsuperpower | |
| 2022-10-21 | added low and high multiply | jjsuperpower | |
| 2022-10-21 | added low and high multiply | jjsuperpower | |
| 2022-10-21 | added jump always, match ISA | jjsuperpower | |
| 2022-10-21 | added enum, updated to ISA | jjsuperpower | |
| 2022-10-21 | incremental update | jjsuperpower | |
| 2022-10-13 | started op codes file | jjsuperpower | |
| 2022-10-13 | started on control | jjsuperpower | |
| 2022-10-13 | misc ( I forgot, ok) | jjsuperpower | |
| 2022-09-24 | fixed some ugly code | jjsuperpower | |
| 2022-09-17 | finished testing jump control | jjsuperpower | |
| 2022-09-17 | made reg more modular | jjsuperpower | |
| 2022-09-17 | added random testing | jjsuperpower | |
| 2022-09-06 | started on jump_ctl block | jjsuperpower | |
| 2022-09-06 | patched security holes UNTESTED | jjsuperpower | |
| 2022-09-06 | consolidated aluflags | jjsuperpower | |
| 2022-09-06 | updated template | jjsuperpower | |
| 2022-09-05 | fixed tb for shiftreg | jjsuperpower | |
| 2022-09-05 | honestly i don't know what I did | jjsuperpower | |
| 2022-09-05 | moveing file around | jjsuperpower | |
| 2022-09-05 | updated testbench format | jjsuperpower | |
| 2022-09-05 | Restructuring and organizing | jjsuperpower | |
| 2022-08-30 | reorganized hdl | jjsuperpower | |
| 2022-08-29 | fixed parity check | jjsuperpower | |
| 2022-08-27 | register partially tested | jjsuperpower | |
| 2022-08-27 | moved interupt control outside reg | jjsuperpower | |
| 2022-08-27 | coded but not tested Register file | jjsuperpower | |
| 2022-08-24 | added odd flag bit | jjsuperpower | |
| 2022-08-24 | Update ALU, added more ops | jjsuperpower | |
| 2022-08-23 | Update the ISA specifications | Danny Holman | |
| Update the spec-sheet for the ISA to reflect current decisions made on 08/23. | |||
| 2022-08-21 | minor change | jjsuperpower | |
| 2022-08-21 | basic alu coded and tested | jjsuperpower | |
| 2022-08-15 | updated ISA | jjsuperpower | |
| 2022-08-15 | added template | jjsuperpower | |
| 2022-08-10 | added make file | jjsuperpower | |
| 2022-08-07 | basic shift register working | jjsuperpower | |
| 2022-08-04 | Updated .gitignore | jjsuperpower | |
| 2022-08-04 | deprecated all myhdl stuff, moving to Amaranth | jjsuperpower | |
| 2022-08-02 | Uploading to remote | jjsuperpower | |
| 2022-06-29 | fixed shift_reg for export | jjsuperpower | |
| 2022-06-28 | vcd file working for cosim | jjsuperpower | |
| 2022-06-28 | added template, ResetSync | jjsuperpower | |
| 2022-06-26 | added template | jjsuperpower | |
| 2022-06-26 | restructured folder | jjsuperpower | |
| 2022-06-26 | shift_reg done | jjsuperpower | |
 |
index : jsanderson/ASAP32.git | |
| Unnamed repository; edit this file 'description' to name the repository. |
| summaryrefslogtreecommitdiff |