diff options
| author | jjsuperpower <jjs29356@gmail.com> | 2022-10-21 23:39:08 -0500 |
|---|---|---|
| committer | jjsuperpower <jjs29356@gmail.com> | 2022-10-21 23:39:08 -0500 |
| commit | fcabfb8f6d900a3c27f811cf345821ebe75fe70c (patch) | |
| tree | a09df2c42fddc8edafbd47b0a65915506a51ce3d | |
| parent | 59910a855955b5bc2cc7fb182c1a099ef4e77502 (diff) | |
added low and high multiply
| -rw-r--r-- | ASAP32-ISA.md | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/ASAP32-ISA.md b/ASAP32-ISA.md index 76599e2..0bdbe2e 100644 --- a/ASAP32-ISA.md +++ b/ASAP32-ISA.md @@ -88,10 +88,12 @@ LSL RD, RS1, RS2 RD = RS1 << RS2 (logical) LSR RD, RS1, RS2 RD = RS1 >> RS2 (logical) ASR RD, RS1, RS2 RD = RS1 >> RS2 - MUL RD, RS1, RS2 RD = RS1 * RS2 - MULU RD, RS1, RS2 RD = RS1 * RS2 (unsigned) - *DIV RD, RS1, RS2 RD = RS1 / RS2 - *DIVU RD, RS1, RS2 RD = RS1 / RS2 (unsigned) + MULL RD, RS1, RS2 RD = (RS1 * RS2) & 0xFFFFFFFF + MULH RD, RS1, RS2 RD = (RS1 * RS2) >> 32 + MULLU RD, RS1, RS2 RD = RS1 * RS2 & 0xFFFFFFFF (unsigned) + MULHU RD, RS1, RS2 RD = (RS1 * RS2) >> 32 (unsigned) + *DIV RD, RS1, RS2 RD = RS1 / RS2 + *DIVU RD, RS1, RS2 RD = RS1 / RS2 (unsigned) LDW RD, RS1, offset RD = MEM[RS1 + offset] LDWR RD, RS1, RS2 RD = MEM[RS1 + RS2] @@ -121,8 +123,10 @@ LSLI RD, RS, IMM RD = RS << IMM (logical) LSRI RD, RS, IMM RD = RS >> IMM (logical) ASRI RD, RS, IMM RD = RS >> IMM - MULI RD, RS, IMM RD = RS * IMM - MULIU RD, RS, IMM RD = RS * IMM (unsigned) + MULIL RD, RS, IMM RD = (RS * IMM) & 0xFFFFFFFF + MULIH RD, RS, IMM RD = (RS * IMM) >> 32 + MULILU RD, RS, IMM RD = (RS * IMM) & 0xFFFFFFFF (unsigned) + MULIHU RD, RS, IMM RD = (RS * IMM) >> 32 (unsigned) DIVI RD, RS, IMM RD = RS / IMM DIVIU RD, RS, IMM RD = RS / IMM (unsigned) |