Age | Commit message (Collapse) | Author | |
---|---|---|---|
2022-08-29 | fixed parity check | jjsuperpower | |
2022-08-27 | register partially tested | jjsuperpower | |
2022-08-27 | moved interupt control outside reg | jjsuperpower | |
2022-08-27 | coded but not tested Register file | jjsuperpower | |
2022-08-24 | added odd flag bit | jjsuperpower | |
2022-08-24 | Update ALU, added more ops | jjsuperpower | |
2022-08-23 | Update the ISA specifications | Danny Holman | |
Update the spec-sheet for the ISA to reflect current decisions made on 08/23. | |||
2022-08-21 | minor change | jjsuperpower | |
2022-08-21 | basic alu coded and tested | jjsuperpower | |
2022-08-15 | updated ISA | jjsuperpower | |
2022-08-15 | added template | jjsuperpower | |
2022-08-10 | added make file | jjsuperpower | |
2022-08-07 | basic shift register working | jjsuperpower | |
2022-08-04 | Updated .gitignore | jjsuperpower | |
2022-08-04 | deprecated all myhdl stuff, moving to Amaranth | jjsuperpower | |
2022-08-02 | Uploading to remote | jjsuperpower | |
2022-06-29 | fixed shift_reg for export | jjsuperpower | |
2022-06-28 | vcd file working for cosim | jjsuperpower | |
2022-06-28 | added template, ResetSync | jjsuperpower | |
2022-06-26 | added template | jjsuperpower | |
2022-06-26 | restructured folder | jjsuperpower | |
2022-06-26 | shift_reg done | jjsuperpower | |
2022-06-24 | before myhdl_wraper | jjsuperpower | |
2022-06-24 | combine shiftreg working | jjsuperpower | |
2022-06-24 | testing multilevel convert | jjsuperpower | |
2022-06-23 | update gitignore | jjsuperpower | |
2022-06-23 | basic myhdl setup working | jjsuperpower | |
2022-06-19 | added hdl folder | jjsuperpower | |