diff options
author | jjsuperpower <jjs29356@gmail.com> | 2022-06-23 23:04:28 -0500 |
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committer | jjsuperpower <jjs29356@gmail.com> | 2022-06-23 23:04:28 -0500 |
commit | 382b73b0989dc00093f4e5daa67d4386722b19fb (patch) | |
tree | 472203a26f5a4b0e573c1528633f90d019d9f2a3 /hdl/testing | |
parent | 26169bec7ae7b85d938f5d3c6e969885f2230541 (diff) |
basic myhdl setup working
Diffstat (limited to 'hdl/testing')
-rw-r--r-- | hdl/testing/.gitignore | 3 | ||||
-rw-r--r-- | hdl/testing/Makefile | 0 | ||||
-rw-r--r-- | hdl/testing/__pycache__/constants.cpython-38.pyc | bin | 0 -> 263 bytes | |||
-rw-r--r-- | hdl/testing/__pycache__/delme.cpython-38.pyc | bin | 0 -> 452 bytes | |||
-rw-r--r-- | hdl/testing/constants.py | 5 | ||||
-rw-r--r-- | hdl/testing/hello_world.py | 129 | ||||
-rw-r--r-- | hdl/testing/inc.v | 39 | ||||
-rwxr-xr-x | hdl/testing/myhdl.vpi | bin | 0 -> 32216 bytes | |||
-rw-r--r-- | hdl/testing/shift_reg.py | 103 | ||||
-rwxr-xr-x | hdl/testing/simulation/ShiftReg.o | 74 | ||||
-rw-r--r-- | hdl/testing/simulation/ShiftReg_sim.vcd | 144 | ||||
-rw-r--r-- | hdl/testing/tb_inc.v | 26 |
12 files changed, 328 insertions, 195 deletions
diff --git a/hdl/testing/.gitignore b/hdl/testing/.gitignore index be78124..16063d7 100644 --- a/hdl/testing/.gitignore +++ b/hdl/testing/.gitignore @@ -1 +1,2 @@ -quartus
\ No newline at end of file +quartus +gen_verilog
\ No newline at end of file diff --git a/hdl/testing/Makefile b/hdl/testing/Makefile new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/hdl/testing/Makefile diff --git a/hdl/testing/__pycache__/constants.cpython-38.pyc b/hdl/testing/__pycache__/constants.cpython-38.pyc Binary files differnew file mode 100644 index 0000000..764603c --- /dev/null +++ b/hdl/testing/__pycache__/constants.cpython-38.pyc diff --git a/hdl/testing/__pycache__/delme.cpython-38.pyc b/hdl/testing/__pycache__/delme.cpython-38.pyc Binary files differnew file mode 100644 index 0000000..db0029e --- /dev/null +++ b/hdl/testing/__pycache__/delme.cpython-38.pyc diff --git a/hdl/testing/constants.py b/hdl/testing/constants.py new file mode 100644 index 0000000..d40d7c1 --- /dev/null +++ b/hdl/testing/constants.py @@ -0,0 +1,5 @@ +SIM_DIR = './simulation/' +GEN_VERILOG = './gen_verilog/' + +IVERILOG = 'iverilog ' +VVP = 'vvp -M ./ -m myhdl '
\ No newline at end of file diff --git a/hdl/testing/hello_world.py b/hdl/testing/hello_world.py deleted file mode 100644 index 2167856..0000000 --- a/hdl/testing/hello_world.py +++ /dev/null @@ -1,129 +0,0 @@ -# from myhdl import block, delay, always, now - -# @block -# def HelloWorld(): - -# @always(delay(10)) -# def say_hello(): -# print("%s Hello World!" % now()) - -# return say_hello - - -# inst = HelloWorld() -# inst.run_sim(30) - -######################################################## - -# from myhdl import block, Signal, delay, always, now - -# @block -# def HelloWorld(): - -# clk = Signal(0) - -# @always(delay(10)) -# def drive_clk(): -# clk.next = not clk - -# @always(clk.posedge) -# def say_hello(): -# print("%s Hello World!" % now()) - -# return drive_clk, say_hello - - -# inst = HelloWorld() -# inst.run_sim(50) - -######################################################## - -# from myhdl import block, always_comb, Signal - -# @block -# def mux(z, a, b, sel): - -# """ Multiplexer. - -# z -- mux output -# a, b -- data inputs -# sel -- control input: select a if asserted, otherwise b - -# """ - -# @always_comb -# def comb(): -# if sel == 1: -# z.next = a -# else: -# z.next = b - -# return comb - -# import random -# from myhdl import block, instance, Signal, intbv, delay - -# random.seed(5) -# randrange = random.randrange - -# @block -# def test_mux(): - -# z, a, b, sel = [Signal(intbv(0)) for i in range(4)] - -# mux_1 = mux(z, a, b, sel) - -# @instance -# def stimulus(): -# print("z a b sel") -# for i in range(12): -# a.next, b.next, sel.next = randrange(8), randrange(8), randrange(2) -# yield delay(10) -# print("%s %s %s %s" % (z, a, b, sel)) - -# return mux_1, stimulus - -# tb = test_mux() -# tb.run_sim() - - -######################################################## - -from myhdl import block, always_seq - -@block -def inc(count, enable, clock, reset): - """ Incrementer with enable. - - count -- output - enable -- control input, increment when 1 - clock -- clock input - reset -- asynchronous reset input - """ - - @always_seq(clock.posedge, reset=reset) - def seq(): - if enable: - count.next = count + 1 - - return seq - -from myhdl import Signal, ResetSignal, modbv - -def convert_inc(hdl): - """Convert inc block to Verilog or VHDL.""" - - m = 8 - - count = Signal(modbv(0)[m:]) - enable = Signal(bool(0)) - clock = Signal(bool(0)) - reset = ResetSignal(0, active=0, isasync=True) - - inc_1 = inc(count, enable, clock, reset) - - inc_1.convert(hdl=hdl) - - -convert_inc(hdl='Verilog') -convert_inc(hdl='VHDL')
\ No newline at end of file diff --git a/hdl/testing/inc.v b/hdl/testing/inc.v deleted file mode 100644 index 2f3291b..0000000 --- a/hdl/testing/inc.v +++ /dev/null @@ -1,39 +0,0 @@ -// File: inc.v -// Generated by MyHDL 0.11 -// Date: Sun Jun 19 22:02:52 2022 - - -`timescale 1ns/10ps - -module inc ( - count, - enable, - clock, - reset -); -// Incrementer with enable. -// -// count -- output -// enable -- control input, increment when 1 -// clock -- clock input -// reset -- asynchronous reset input - -output [7:0] count; -reg [7:0] count; -input enable; -input clock; -input reset; - - -always @(posedge clock, negedge reset) begin: INC_SEQ - if (reset == 0) begin - count <= 0; - end - else begin - if (enable) begin - count <= (count + 1); - end - end -end - -endmodule diff --git a/hdl/testing/myhdl.vpi b/hdl/testing/myhdl.vpi Binary files differnew file mode 100755 index 0000000..1b9d393 --- /dev/null +++ b/hdl/testing/myhdl.vpi diff --git a/hdl/testing/shift_reg.py b/hdl/testing/shift_reg.py index e69de29..a98fb4c 100644 --- a/hdl/testing/shift_reg.py +++ b/hdl/testing/shift_reg.py @@ -0,0 +1,103 @@ +from fileinput import filename +from myhdl import * +import os + +from sympy import Si + +from constants import * + +class ShiftReg(): + def __init__(self): + self.class_name = self.__class__.__name__ + + # Main code, this is the actual logic + @staticmethod + @block + def logic(reset: Signal, clk: Signal, in0: Signal, out0: Signal, left_rigt: bool = 1, width: int = 8): + + @always_seq(clk.posedge, reset=reset) + def shifter(): + if not left_rigt: + out0.next[width:1] = out0[width-1:0] + out0.next[0] = in0 + else: + out0.next[width-1:0] = out0[width:1] + out0.next[width-1] = in0 + + return shifter + + + @block + def tb(self, func): + reset = ResetSignal(0, 0, True) + clk = Signal(bool(0)) + in0 = Signal(0) + out0 = Signal(modbv(0)[8:]) + + dut = getattr(self, str(func))(reset=reset, clk=clk, in0=in0, out0=out0) + + @always(delay(2)) + def clock_gen(): + clk.next = not clk + + @instance + def monitor(): + while True: + yield clk.posedge + yield delay(1) + print(bin(out0, 8)) + + @instance + def stimulus(): + yield clk.negedge + reset.next = 1 + + for i in range(9): + yield clk.negedge + in0.next = 1 + + for i in range(9): + yield clk.negedge + in0.next = 0 + + raise StopSimulation + + return dut, clock_gen, monitor, stimulus + + def convert(self): + reset = ResetSignal(0, 0, True) + clk = Signal(bool(0)) + in0 = Signal(bool(0)) + out0 = Signal(modbv(0)[8:]) + + inst = self.logic(reset=reset, clk=clk, in0=in0, out0=out0) + inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}") + + + # This function links myhdl to icarus verilog sim + def _cosim(self, reset: Signal, clk: Signal, in0: Signal, out0: Signal): #these should have the same signals as logic(), + + iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v" + vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o" + + signals = locals() + signals.pop('self', None) + signals.pop('iverilog_cmd', None) + signals.pop('vvp_cmd', None) + + os.system(iverilog_cmd) + return Cosimulation(vvp_cmd, **signals) + + def sim(self): + tb = self.tb('logic') + tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim") + tb.run_sim() + + def cosim(self): + tb = self.tb('_cosim') + tb.run_sim() + +hdl = ShiftReg() +hdl.sim() +hdl.convert() +hdl.cosim() diff --git a/hdl/testing/simulation/ShiftReg.o b/hdl/testing/simulation/ShiftReg.o new file mode 100755 index 0000000..e5d3c84 --- /dev/null +++ b/hdl/testing/simulation/ShiftReg.o @@ -0,0 +1,74 @@ +#! /usr/local/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1545-g93397e723)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 11; +:vpi_module "/usr/local/lib64/ivl/system.vpi"; +:vpi_module "/usr/local/lib64/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/local/lib64/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/local/lib64/ivl/v2005_math.vpi"; +:vpi_module "/usr/local/lib64/ivl/va_math.vpi"; +S_0xf39680 .scope module, "tb_ShiftReg" "tb_ShiftReg" 2 1; + .timescale -9 -11; +v0xf4a460_0 .var "clk", 0 0; +v0xf4a520_0 .var "in0", 0 0; +v0xf4a5f0_0 .net "out0", 7 0, v0xf4a200_0; 1 drivers +v0xf4a6f0_0 .var "reset", 0 0; +S_0xf39810 .scope module, "dut" "ShiftReg" 2 19, 3 8 0, S_0xf39680; + .timescale -9 -11; + .port_info 0 /INPUT 1 "reset"; + .port_info 1 /INPUT 1 "clk"; + .port_info 2 /INPUT 1 "in0"; + .port_info 3 /OUTPUT 8 "out0"; +v0xf39a60_0 .net "clk", 0 0, v0xf4a460_0; 1 drivers +v0xf4a140_0 .net "in0", 0 0, v0xf4a520_0; 1 drivers +v0xf4a200_0 .var "out0", 7 0; +v0xf4a2f0_0 .net "reset", 0 0, v0xf4a6f0_0; 1 drivers +E_0xf23bd0/0 .event negedge, v0xf4a2f0_0; +E_0xf23bd0/1 .event posedge, v0xf39a60_0; +E_0xf23bd0 .event/or E_0xf23bd0/0, E_0xf23bd0/1; +S_0xefdcf0 .scope begin, "SHIFTREG_SHIFTER" "SHIFTREG_SHIFTER" 3 25, 3 25 0, S_0xf39810; + .timescale -9 -11; + .scope S_0xf39810; +T_0 ; + %wait E_0xf23bd0; + %fork t_1, S_0xefdcf0; + %jmp t_0; + .scope S_0xefdcf0; +t_1 ; + %load/vec4 v0xf4a2f0_0; + %pad/u 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_0.0, 4; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0xf4a200_0, 0; + %jmp T_0.1; +T_0.0 ; + %load/vec4 v0xf4a200_0; + %parti/s 7, 1, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xf4a200_0, 4, 5; + %load/vec4 v0xf4a140_0; + %ix/load 4, 7, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xf4a200_0, 4, 5; +T_0.1 ; + %end; + .scope S_0xf39810; +t_0 %join; + %jmp T_0; + .thread T_0; + .scope S_0xf39680; +T_1 ; + %vpi_call 2 9 "$from_myhdl", v0xf4a6f0_0, v0xf4a460_0, v0xf4a520_0 {0 0 0}; + %vpi_call 2 14 "$to_myhdl", v0xf4a5f0_0 {0 0 0}; + %end; + .thread T_1; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + "<interactive>"; + "./gen_verilog/tb_ShiftReg.v"; + "./gen_verilog/ShiftReg.v"; diff --git a/hdl/testing/simulation/ShiftReg_sim.vcd b/hdl/testing/simulation/ShiftReg_sim.vcd new file mode 100644 index 0000000..f9d6dd4 --- /dev/null +++ b/hdl/testing/simulation/ShiftReg_sim.vcd @@ -0,0 +1,144 @@ +$date + Thu Jun 23 23:03:17 2022 +$end +$version + MyHDL 0.11 +$end +$timescale + 1ns +$end + +$scope module tb $end +$var reg 1 ! clk $end +$var real 1 " in0 $end +$var reg 8 # out0 $end +$var reg 1 $ reset $end +$scope module logic0 $end +$var reg 1 $ reset $end +$var reg 1 ! clk $end +$var real 1 " in0 $end +$var reg 8 # out0 $end +$upscope $end +$upscope $end + +$enddefinitions $end +$dumpvars +0! +s0 " +b00000000 # +0$ +$end +#2 +1! +#3 +#4 +0! +1$ +#6 +1! +#7 +#8 +0! +s1 " +#10 +1! +b10000000 # +#11 +#12 +0! +#14 +1! +b11000000 # +#15 +#16 +0! +#18 +1! +b11100000 # +#19 +#20 +0! +#22 +1! +b11110000 # +#23 +#24 +0! +#26 +1! +b11111000 # +#27 +#28 +0! +#30 +1! +b11111100 # +#31 +#32 +0! +#34 +1! +b11111110 # +#35 +#36 +0! +#38 +1! +b11111111 # +#39 +#40 +0! +#42 +1! +#43 +#44 +0! +s0 " +#46 +1! +b01111111 # +#47 +#48 +0! +#50 +1! +b00111111 # +#51 +#52 +0! +#54 +1! +b00011111 # +#55 +#56 +0! +#58 +1! +b00001111 # +#59 +#60 +0! +#62 +1! +b00000111 # +#63 +#64 +0! +#66 +1! +b00000011 # +#67 +#68 +0! +#70 +1! +b00000001 # +#71 +#72 +0! +#74 +1! +b00000000 # +#75 +#76 +0! diff --git a/hdl/testing/tb_inc.v b/hdl/testing/tb_inc.v deleted file mode 100644 index c0cf480..0000000 --- a/hdl/testing/tb_inc.v +++ /dev/null @@ -1,26 +0,0 @@ -module tb_inc; - -wire [7:0] count; -reg enable; -reg clock; -reg reset; - -initial begin - $from_myhdl( - enable, - clock, - reset - ); - $to_myhdl( - count - ); -end - -inc dut( - count, - enable, - clock, - reset -); - -endmodule |