hdl/testing/tb_inc.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

module tb_inc;

wire [7:0] count;
reg enable;
reg clock;
reg reset;

initial begin
    $from_myhdl(
        enable,
        clock,
        reset
    );
    $to_myhdl(
        count
    );
end

inc dut(
    count,
    enable,
    clock,
    reset
);

endmodule