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#! /usr/local/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1545-g93397e723)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 11;
:vpi_module "/usr/local/lib64/ivl/system.vpi";
:vpi_module "/usr/local/lib64/ivl/vhdl_sys.vpi";
:vpi_module "/usr/local/lib64/ivl/vhdl_textio.vpi";
:vpi_module "/usr/local/lib64/ivl/v2005_math.vpi";
:vpi_module "/usr/local/lib64/ivl/va_math.vpi";
S_0xf39680 .scope module, "tb_ShiftReg" "tb_ShiftReg" 2 1;
.timescale -9 -11;
v0xf4a460_0 .var "clk", 0 0;
v0xf4a520_0 .var "in0", 0 0;
v0xf4a5f0_0 .net "out0", 7 0, v0xf4a200_0; 1 drivers
v0xf4a6f0_0 .var "reset", 0 0;
S_0xf39810 .scope module, "dut" "ShiftReg" 2 19, 3 8 0, S_0xf39680;
.timescale -9 -11;
.port_info 0 /INPUT 1 "reset";
.port_info 1 /INPUT 1 "clk";
.port_info 2 /INPUT 1 "in0";
.port_info 3 /OUTPUT 8 "out0";
v0xf39a60_0 .net "clk", 0 0, v0xf4a460_0; 1 drivers
v0xf4a140_0 .net "in0", 0 0, v0xf4a520_0; 1 drivers
v0xf4a200_0 .var "out0", 7 0;
v0xf4a2f0_0 .net "reset", 0 0, v0xf4a6f0_0; 1 drivers
E_0xf23bd0/0 .event negedge, v0xf4a2f0_0;
E_0xf23bd0/1 .event posedge, v0xf39a60_0;
E_0xf23bd0 .event/or E_0xf23bd0/0, E_0xf23bd0/1;
S_0xefdcf0 .scope begin, "SHIFTREG_SHIFTER" "SHIFTREG_SHIFTER" 3 25, 3 25 0, S_0xf39810;
.timescale -9 -11;
.scope S_0xf39810;
T_0 ;
%wait E_0xf23bd0;
%fork t_1, S_0xefdcf0;
%jmp t_0;
.scope S_0xefdcf0;
t_1 ;
%load/vec4 v0xf4a2f0_0;
%pad/u 32;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.0, 4;
%pushi/vec4 0, 0, 8;
%assign/vec4 v0xf4a200_0, 0;
%jmp T_0.1;
T_0.0 ;
%load/vec4 v0xf4a200_0;
%parti/s 7, 1, 2;
%ix/load 4, 0, 0;
%ix/load 5, 0, 0;
%flag_set/imm 4, 0;
%assign/vec4/off/d v0xf4a200_0, 4, 5;
%load/vec4 v0xf4a140_0;
%ix/load 4, 7, 0;
%ix/load 5, 0, 0;
%flag_set/imm 4, 0;
%assign/vec4/off/d v0xf4a200_0, 4, 5;
T_0.1 ;
%end;
.scope S_0xf39810;
t_0 %join;
%jmp T_0;
.thread T_0;
.scope S_0xf39680;
T_1 ;
%vpi_call 2 9 "$from_myhdl", v0xf4a6f0_0, v0xf4a460_0, v0xf4a520_0 {0 0 0};
%vpi_call 2 14 "$to_myhdl", v0xf4a5f0_0 {0 0 0};
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"./gen_verilog/tb_ShiftReg.v";
"./gen_verilog/ShiftReg.v";
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