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# from myhdl import block, delay, always, now
# @block
# def HelloWorld():
# @always(delay(10))
# def say_hello():
# print("%s Hello World!" % now())
# return say_hello
# inst = HelloWorld()
# inst.run_sim(30)
########################################################
# from myhdl import block, Signal, delay, always, now
# @block
# def HelloWorld():
# clk = Signal(0)
# @always(delay(10))
# def drive_clk():
# clk.next = not clk
# @always(clk.posedge)
# def say_hello():
# print("%s Hello World!" % now())
# return drive_clk, say_hello
# inst = HelloWorld()
# inst.run_sim(50)
########################################################
# from myhdl import block, always_comb, Signal
# @block
# def mux(z, a, b, sel):
# """ Multiplexer.
# z -- mux output
# a, b -- data inputs
# sel -- control input: select a if asserted, otherwise b
# """
# @always_comb
# def comb():
# if sel == 1:
# z.next = a
# else:
# z.next = b
# return comb
# import random
# from myhdl import block, instance, Signal, intbv, delay
# random.seed(5)
# randrange = random.randrange
# @block
# def test_mux():
# z, a, b, sel = [Signal(intbv(0)) for i in range(4)]
# mux_1 = mux(z, a, b, sel)
# @instance
# def stimulus():
# print("z a b sel")
# for i in range(12):
# a.next, b.next, sel.next = randrange(8), randrange(8), randrange(2)
# yield delay(10)
# print("%s %s %s %s" % (z, a, b, sel))
# return mux_1, stimulus
# tb = test_mux()
# tb.run_sim()
########################################################
from myhdl import block, always_seq
@block
def inc(count, enable, clock, reset):
""" Incrementer with enable.
count -- output
enable -- control input, increment when 1
clock -- clock input
reset -- asynchronous reset input
"""
@always_seq(clock.posedge, reset=reset)
def seq():
if enable:
count.next = count + 1
return seq
from myhdl import Signal, ResetSignal, modbv
def convert_inc(hdl):
"""Convert inc block to Verilog or VHDL."""
m = 8
count = Signal(modbv(0)[m:])
enable = Signal(bool(0))
clock = Signal(bool(0))
reset = ResetSignal(0, active=0, isasync=True)
inc_1 = inc(count, enable, clock, reset)
inc_1.convert(hdl=hdl)
convert_inc(hdl='Verilog')
convert_inc(hdl='VHDL')
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