2 files changed, 36 insertions, 4 deletions
diff --git a/hdl/shift_reg.py b/hdl/shift_reg.py
index dedc56b..40af39b 100644
--- a/hdl/shift_reg.py
+++ b/hdl/shift_reg.py
@@ -1,8 +1,4 @@
-import sys
-from wsgiref.util import shift_path_info
 from amaranth import *
-from amaranth.back import verilog, cxxrtl
-from amaranth.cli import main
 from amaranth.sim import Simulator, Settle, Delay
 
 from utils import cmd
diff --git a/hdl/template.py b/hdl/template.py
new file mode 100644
index 0000000..5df554c
--- /dev/null
+++ b/hdl/template.py
@@ -0,0 +1,36 @@
+from amaranth import *
+from amaranth.sim import Simulator, Settle, Delay
+
+from utils import cmd
+
+class Template(Elaboratable):
+    def __init__(self):
+        ...
+
+        self.ports = [...]
+
+    def elaborate(self, platform):
+        m = Module()
+
+        ...
+
+        return m
+
+def test(filename="out.vcd"):
+    dut = ...
+
+    def proc1():
+        ...
+
+
+    sim = Simulator(dut)
+    sim.add_clock(1e-6)
+    sim.add_sync_process(proc1)
+    
+    with sim.write_vcd(filename):
+        sim.run()
+
+
+if __name__ == '__main__':
+    shift_reg = Template(8)
+    cmd(shift_reg, test)
+\ No newline at end of file