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from amaranth import *
from amaranth.sim import Simulator, Settle, Delay
from utils import cmd
class Template(Elaboratable):
def __init__(self):
...
self.ports = [...]
def elaborate(self, platform):
m = Module()
...
return m
def test(filename="out.vcd"):
dut = ...
def proc1():
...
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_sync_process(proc1)
with sim.write_vcd(filename):
sim.run()
if __name__ == '__main__':
shift_reg = Template(8)
cmd(shift_reg, test)
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