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authorjjsuperpower <jjs29356@gmail.com>2022-06-26 09:26:20 -0500
committerjjsuperpower <jjs29356@gmail.com>2022-06-26 09:26:20 -0500
commitf4407898d3d74be98cdf1a0308c779cd842364ab (patch)
tree9e17c6560543b3c657e3f79836bb37222e8c4bea /hdl/testing/Makefile
parentaf47ba80d5db24163feb378c52a20639e2532580 (diff)
shift_reg done
Diffstat (limited to 'hdl/testing/Makefile')
-rw-r--r--hdl/testing/Makefile12
1 files changed, 12 insertions, 0 deletions
diff --git a/hdl/testing/Makefile b/hdl/testing/Makefile
index e69de29..5e6391c 100644
--- a/hdl/testing/Makefile
+++ b/hdl/testing/Makefile
@@ -0,0 +1,12 @@
+
+HDL = shift_reg.py
+
+
+test:
+ py.test --disable-pytest-warnings -v $(HDL)
+
+test-w:
+ py.test -v $(HDL)
+
+clean:
+ $(RM) -rf simulation/* gen_verilog/* __pycache__/* .pytest_cache/* \ No newline at end of file