From f4407898d3d74be98cdf1a0308c779cd842364ab Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Sun, 26 Jun 2022 09:26:20 -0500 Subject: shift_reg done --- hdl/testing/Makefile | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'hdl/testing/Makefile') diff --git a/hdl/testing/Makefile b/hdl/testing/Makefile index e69de29..5e6391c 100644 --- a/hdl/testing/Makefile +++ b/hdl/testing/Makefile @@ -0,0 +1,12 @@ + +HDL = shift_reg.py + + +test: + py.test --disable-pytest-warnings -v $(HDL) + +test-w: + py.test -v $(HDL) + +clean: + $(RM) -rf simulation/* gen_verilog/* __pycache__/* .pytest_cache/* \ No newline at end of file -- cgit v1.2.3