diff options
author | jjsuperpower <jjs29356@gmail.com> | 2022-08-29 20:39:19 -0500 |
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committer | jjsuperpower <jjs29356@gmail.com> | 2022-08-29 20:39:19 -0500 |
commit | 5a7dedee172dbb30f1053e303a5d984ef96fd001 (patch) | |
tree | 1916d139371d079d82b0c6b4791adbcc9021e328 /hdl/template.py | |
parent | c169161c9eeb8421abd28183067e41231bf3a8a0 (diff) |
fixed parity check
Diffstat (limited to 'hdl/template.py')
-rw-r--r-- | hdl/template.py | 36 |
1 files changed, 0 insertions, 36 deletions
diff --git a/hdl/template.py b/hdl/template.py deleted file mode 100644 index 64f0655..0000000 --- a/hdl/template.py +++ /dev/null @@ -1,36 +0,0 @@ -from amaranth import * -from amaranth.sim import Simulator, Settle, Delay - -from utils import cmd - -class Template(Elaboratable): - def __init__(self): - ... - - self.ports = [...] - - def elaborate(self, platform): - m = Module() - - ... - - return m - -def test(filename="out.vcd"): - dut = ... - - def proc1(): - ... - - - sim = Simulator(dut) - sim.add_clock(1e-6) - sim.add_sync_process(proc1) - - with sim.write_vcd(filename): - sim.run() - - -if __name__ == '__main__': - shift_reg = Template(...) - cmd(shift_reg, test)
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