diff options
author | jjsuperpower <jjs29356@gmail.com> | 2022-09-24 15:04:21 -0500 |
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committer | jjsuperpower <jjs29356@gmail.com> | 2022-09-24 15:04:21 -0500 |
commit | f2fa10954b481315e749ccb2da8ceb9bcce91723 (patch) | |
tree | a66220594c58582f36abf6980fc8da49b506c972 /hdl/core/jump_ctl.py | |
parent | 5653b767f0dd94cb0441dd326c4c2fb795b996c8 (diff) |
fixed some ugly code
Diffstat (limited to 'hdl/core/jump_ctl.py')
-rw-r--r-- | hdl/core/jump_ctl.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hdl/core/jump_ctl.py b/hdl/core/jump_ctl.py index 6a7cf1b..468c2e3 100644 --- a/hdl/core/jump_ctl.py +++ b/hdl/core/jump_ctl.py @@ -2,7 +2,7 @@ from amaranth import * from amaranth.sim import Simulator, Settle, Delay from enum import Enum, unique -from hdl.utils import cmd, step, eval, sim, rand_bits_mix +from hdl.utils import * from hdl.lib.in_out_buff import InOutBuff # used for timing analysis from hdl.core.alu import ALUFlags, ALU, AluOpCodes #ALUOpCodes is for simulation only, not used in hardware @@ -20,7 +20,7 @@ class JumpOpCodes(Enum): class JumpCtl(Elaboratable): def __init__(self, **kargs): - self.alu_flags = Signal(ALU().alu_flags.width, reset_less=True) + self.alu_flags = Signal(len(ALUFlags), reset_less=True) self.op = Signal(3, reset_less=True) self.signed_bits = Signal(2, reset_less=True) |