fixed some ugly code

3 files changed, 9 insertions, 8 deletions

diff --git a/hdl/core/alu.py b/hdl/core/alu.py
index b4261bd..f8a1a25 100644
--- a/hdl/core/alu.py
+++ b/hdl/core/alu.py
@@ -2,7 +2,7 @@ from amaranth import *
 from amaranth.sim import Simulator, Settle, Delay
 from enum import Enum, unique
 
-from hdl.utils import cmd, step, sim
+from hdl.utils import *
 from hdl.lib.in_out_buff import InOutBuff
 
 @unique
@@ -31,11 +31,12 @@ class ALUFlags(Enum):
     negative = 3
 
 class ALU(Elaboratable):
+
     def __init__(self, **kargs):
         self.in1 = Signal(32, reset_less=True)
         self.in2 = Signal(32, reset_less=True)
         self.c_in = Signal(1)
-        self.op = Signal(4, reset_less=True)
+        self.op = Signal(e2s(AluOpCodes), reset_less=True)
 
         self.tmp = Signal(33, reset_less=True)
 
@@ -44,7 +45,7 @@ class ALU(Elaboratable):
         self.zero = Signal(1, reset_less=True)
         self.neg = Signal(1, reset_less=True)
 
-        self.alu_flags = Signal(4, reset_less=True)
+        self.alu_flags = Signal(len(ALUFlags), reset_less=True) # alu flags is one hot
         self.out = Signal(32, reset_less=True)
 
         self.sim = kargs["sim"] if "sim" in kargs else None
diff --git a/hdl/core/jump_ctl.py b/hdl/core/jump_ctl.py
index 6a7cf1b..468c2e3 100644
--- a/hdl/core/jump_ctl.py
+++ b/hdl/core/jump_ctl.py
@@ -2,7 +2,7 @@ from amaranth import *
 from amaranth.sim import Simulator, Settle, Delay
 from enum import Enum, unique
 
-from hdl.utils import cmd, step, eval, sim, rand_bits_mix
+from hdl.utils import *
 from hdl.lib.in_out_buff import InOutBuff   # used for timing analysis
 
 from hdl.core.alu import ALUFlags, ALU, AluOpCodes  #ALUOpCodes is for simulation only, not used in hardware
@@ -20,7 +20,7 @@ class JumpOpCodes(Enum):
 class JumpCtl(Elaboratable):
     def __init__(self, **kargs):
         
-        self.alu_flags = Signal(ALU().alu_flags.width, reset_less=True)
+        self.alu_flags = Signal(len(ALUFlags), reset_less=True)
         self.op = Signal(3, reset_less=True)
         self.signed_bits = Signal(2, reset_less=True)
 
diff --git a/hdl/core/reg.py b/hdl/core/reg.py
index 0fee155..3526408 100644
--- a/hdl/core/reg.py
+++ b/hdl/core/reg.py
@@ -3,9 +3,9 @@ from amaranth import *
 from amaranth.sim import Settle
 
 from hdl.lib.in_out_buff import InOutBuff
-from hdl.utils import cmd, step, sim
+from hdl.utils import *
 
-from hdl.core.alu import ALUFlags, ALU
+from hdl.core.alu import ALUFlags
 
 
 @unique
@@ -32,7 +32,7 @@ class Reg(Elaboratable):
         self.rs1_addr = Signal(4)
         self.rs2_addr = Signal(4)
 
-        self.alu_flgs = Signal(ALU().alu_flags.width)   # flags from alu
+        self.alu_flgs = Signal(len(ALUFlags))   # flags from alu
 
         # these signals should be used one hot only
         self.int_sig = Signal(1)    # unconditional interrupt