diff options
author | jjsuperpower <jjs29356@gmail.com> | 2022-06-26 11:11:43 -0500 |
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committer | jjsuperpower <jjs29356@gmail.com> | 2022-06-26 11:11:43 -0500 |
commit | 5de4d07c6db81a9ed21cd39aaef229fb94c4bb6b (patch) | |
tree | a73138c38bd71079ffcebc73fe67a1545c6d4fa4 /hdl_lab/hdl/template.py | |
parent | 987134966d0c3ab9b1a5775c8f01fa707408780b (diff) |
added template
Diffstat (limited to 'hdl_lab/hdl/template.py')
-rw-r--r-- | hdl_lab/hdl/template.py | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/hdl_lab/hdl/template.py b/hdl_lab/hdl/template.py new file mode 100644 index 0000000..09a6f7f --- /dev/null +++ b/hdl_lab/hdl/template.py @@ -0,0 +1,67 @@ +from typing import Callable +from myhdl import * +from myhdl_wrap import Myhdl_Wrapper + +import random +from random import randint + +random.seed(63) + +class Template(Myhdl_Wrapper): + def __init__(self): + super().__init__() + + # Main code, this is the actual logic + @staticmethod + @block + def Template(args): # this must be the same name as the class name + + @instance + def logic(): + ... + + return logic + + + @block + def tb(self, func: Callable): + reset = Signal(False) + clk = Signal(bool(0)) + ... + + dut = func(..., clk=clk, reset=reset) + + @always(delay(...)) + def clock_gen(): + clk.next = not clk + + @instance + def monitor(): + ... + + @instance + def stimulus(): + ... + + raise StopSimulation + + + return dut, clock_gen, monitor, stimulus + + def export(self): + reset = Signal(False) + clk = Signal(bool(0)) + ... + + # assigning signals, kargs only + self._export(..., clk=clk, reset=reset) + + +def test_template_sim(): + hdl = Template() + hdl.sim() + +def test_template_cosim(): + hdl = Template() + hdl.export() + hdl.cosim() |