fixed shift_reg for export

1 files changed, 3 insertions, 3 deletions

diff --git a/hdl_lab/hdl/shift_reg.py b/hdl_lab/hdl/shift_reg.py
index d463a9f..9c1c6be 100644
--- a/hdl_lab/hdl/shift_reg.py
+++ b/hdl_lab/hdl/shift_reg.py
@@ -27,10 +27,10 @@ class ShiftReg(Myhdl_Wrapper):
                 else:
                     if not left_right:
                         out0.next[width:1] = out0[width-1:0]
-                        out0.next[0] = in0
+                        out0.next[1:0] = in0
                     else:
                         out0.next[width-1:0] = out0[width:1]
-                        out0.next[width-1] = in0
+                        out0.next[width:width-1] = in0
 
         return shifter
 
@@ -100,7 +100,7 @@ class ShiftReg(Myhdl_Wrapper):
     def export(self):
         reset = Signal(False)
         clk = Signal(bool(0))
-        load = Signal(intbv(0x00)[8:])
+        load = Signal(intbv(0xA5)[8:])
         in0 = Signal(bool(0))
         out0 = Signal(modbv(int(load))[8:])
         left_right = Signal(bool(0))