diff options
| -rw-r--r-- | hdl_lab/hdl/multiply.py | 3 | ||||
| -rw-r--r-- | hdl_lab/hdl/reset_sync.py | 2 | ||||
| -rw-r--r-- | hdl_lab/hdl/shift_reg.py | 6 |
3 files changed, 3 insertions, 8 deletions
diff --git a/hdl_lab/hdl/multiply.py b/hdl_lab/hdl/multiply.py index 2d275a8..015f67a 100644 --- a/hdl_lab/hdl/multiply.py +++ b/hdl_lab/hdl/multiply.py @@ -203,6 +203,3 @@ def test_template_cosim(): hdl = Multiply() hdl.export() hdl.cosim() - -# test_template_sim() -test_template_cosim()
\ No newline at end of file diff --git a/hdl_lab/hdl/reset_sync.py b/hdl_lab/hdl/reset_sync.py index 04ccdeb..af03075 100644 --- a/hdl_lab/hdl/reset_sync.py +++ b/hdl_lab/hdl/reset_sync.py @@ -107,5 +107,3 @@ def test_reset_sync_cosim(): hdl.export() hdl.cosim() -test_reset_sync_sim() -test_reset_sync_cosim() diff --git a/hdl_lab/hdl/shift_reg.py b/hdl_lab/hdl/shift_reg.py index d463a9f..9c1c6be 100644 --- a/hdl_lab/hdl/shift_reg.py +++ b/hdl_lab/hdl/shift_reg.py @@ -27,10 +27,10 @@ class ShiftReg(Myhdl_Wrapper): else: if not left_right: out0.next[width:1] = out0[width-1:0] - out0.next[0] = in0 + out0.next[1:0] = in0 else: out0.next[width-1:0] = out0[width:1] - out0.next[width-1] = in0 + out0.next[width:width-1] = in0 return shifter @@ -100,7 +100,7 @@ class ShiftReg(Myhdl_Wrapper): def export(self): reset = Signal(False) clk = Signal(bool(0)) - load = Signal(intbv(0x00)[8:]) + load = Signal(intbv(0xA5)[8:]) in0 = Signal(bool(0)) out0 = Signal(modbv(int(load))[8:]) left_right = Signal(bool(0)) |