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| author | jjsuperpower <jjs29356@gmail.com> | 2022-06-28 23:14:28 -0500 |
|---|---|---|
| committer | jjsuperpower <jjs29356@gmail.com> | 2022-06-28 23:14:28 -0500 |
| commit | 346307134958f5e4c0db141993d62b3b5c28996c (patch) | |
| tree | 3ced2223b5cbf3d7279df712d54e4030f3027c1a /hdl_lab/Makefile | |
| parent | 5de4d07c6db81a9ed21cd39aaef229fb94c4bb6b (diff) | |
added template, ResetSync
Diffstat (limited to 'hdl_lab/Makefile')
| -rw-r--r-- | hdl_lab/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hdl_lab/Makefile b/hdl_lab/Makefile index a85bbd8..10ace11 100644 --- a/hdl_lab/Makefile +++ b/hdl_lab/Makefile @@ -10,4 +10,4 @@ test-w: py.test -v $(HDL) clean: - $(RM) -rf simulation/* gen_verilog/* hdl/__pycache__/* .pytest_cache/*
\ No newline at end of file + $(RM) -rf simulation/* gen_verilog/* hdl/__pycache__ .pytest_cache
\ No newline at end of file |