From 346307134958f5e4c0db141993d62b3b5c28996c Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Tue, 28 Jun 2022 23:14:28 -0500 Subject: added template, ResetSync --- hdl_lab/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hdl_lab/Makefile') diff --git a/hdl_lab/Makefile b/hdl_lab/Makefile index a85bbd8..10ace11 100644 --- a/hdl_lab/Makefile +++ b/hdl_lab/Makefile @@ -10,4 +10,4 @@ test-w: py.test -v $(HDL) clean: - $(RM) -rf simulation/* gen_verilog/* hdl/__pycache__/* .pytest_cache/* \ No newline at end of file + $(RM) -rf simulation/* gen_verilog/* hdl/__pycache__ .pytest_cache \ No newline at end of file -- cgit v1.2.3