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authorjjsuperpower <jjs29356@gmail.com>2022-06-28 23:59:02 -0500
committerjjsuperpower <jjs29356@gmail.com>2022-06-28 23:59:02 -0500
commit7947465eba567b1982e81e38771328d8d1303fce (patch)
tree04ca046242c31a3d21d73b62cc58a239c57b9e2c /hdl_lab/.gitignore
parent346307134958f5e4c0db141993d62b3b5c28996c (diff)
vcd file working for cosim
Diffstat (limited to 'hdl_lab/.gitignore')
-rw-r--r--hdl_lab/.gitignore1
1 files changed, 1 insertions, 0 deletions
diff --git a/hdl_lab/.gitignore b/hdl_lab/.gitignore
index bae8235..3f63f69 100644
--- a/hdl_lab/.gitignore
+++ b/hdl_lab/.gitignore
@@ -3,4 +3,5 @@ gen_verilog
simulation
.vscode
__pycache__
+**__pycache__
.pytest_cache \ No newline at end of file