From 7947465eba567b1982e81e38771328d8d1303fce Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Tue, 28 Jun 2022 23:59:02 -0500 Subject: vcd file working for cosim --- hdl_lab/.gitignore | 1 + 1 file changed, 1 insertion(+) (limited to 'hdl_lab/.gitignore') diff --git a/hdl_lab/.gitignore b/hdl_lab/.gitignore index bae8235..3f63f69 100644 --- a/hdl_lab/.gitignore +++ b/hdl_lab/.gitignore @@ -3,4 +3,5 @@ gen_verilog simulation .vscode __pycache__ +**__pycache__ .pytest_cache \ No newline at end of file -- cgit v1.2.3