From 5a7dedee172dbb30f1053e303a5d984ef96fd001 Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Mon, 29 Aug 2022 20:39:19 -0500 Subject: fixed parity check --- hdl/core.py | 26 ++++++++++++++++++++------ hdl/template.py | 36 ------------------------------------ hdl/template.py.txt | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 42 deletions(-) delete mode 100644 hdl/template.py create mode 100644 hdl/template.py.txt (limited to 'hdl') diff --git a/hdl/core.py b/hdl/core.py index 9355bf3..2b7a977 100644 --- a/hdl/core.py +++ b/hdl/core.py @@ -277,7 +277,9 @@ def test_reg(filename="reg.vcd"): yield dut.rd_addr.eq(dut.zx.idx) # can be anything except flg register yield dut.rd.eq(0xFFFF0000) # this does not matter yield from step() - assert (yield dut.flg) == (0x0000001f ), f'ERROR: alu is not writing to flg register' + assert (yield dut.flg) == (yield dut.alu_flgs), f'ERROR: alu is not writing to flg register' + + sim = Simulator(dut) @@ -431,7 +433,7 @@ class ALU(Elaboratable): m.d.comb += self.out.eq(self.tmp[0:32]) m.d.comb += self.neg.eq(self.out[31]) m.d.comb += self.zero.eq(self.out == 0) - m.d.comb += self.odd.eq(self.out[0]) + m.d.comb += self.odd.eq(self.out.xor()) # 1 if odd number of bits, 0 if even return m @@ -551,6 +553,18 @@ def test_alu(filename="alu.vcd"): yield from sub_proc(0, 1) # add 0 to 0 out = yield dut.zero assert out == 0, f'ERROR: {out} != {0}' + + # test odd + yield dut.op.eq(AluOpCodes.add.value) + yield from sub_proc(0, 0xAAAAAAAA) # add 0 to 0 + out = yield dut.odd + assert out == 0, f'ERROR: {out} != {0}' + + # test odd + yield dut.op.eq(AluOpCodes.add.value) + yield from sub_proc(0, 0xAAAAAAAB) # add 0 to 0 + out = yield dut.odd + assert out == 1, f'ERROR: {out} != {1}' sim = Simulator(dut) @@ -563,8 +577,8 @@ def test_alu(filename="alu.vcd"): if __name__ == '__main__': - reg = Reg() - cmd(reg, test_reg) + # reg = Reg() + # cmd(reg, test_reg) - # hdl = ALU() - # cmd(hdl, test_alu) + hdl = ALU() + cmd(hdl, test_alu) diff --git a/hdl/template.py b/hdl/template.py deleted file mode 100644 index 64f0655..0000000 --- a/hdl/template.py +++ /dev/null @@ -1,36 +0,0 @@ -from amaranth import * -from amaranth.sim import Simulator, Settle, Delay - -from utils import cmd - -class Template(Elaboratable): - def __init__(self): - ... - - self.ports = [...] - - def elaborate(self, platform): - m = Module() - - ... - - return m - -def test(filename="out.vcd"): - dut = ... - - def proc1(): - ... - - - sim = Simulator(dut) - sim.add_clock(1e-6) - sim.add_sync_process(proc1) - - with sim.write_vcd(filename): - sim.run() - - -if __name__ == '__main__': - shift_reg = Template(...) - cmd(shift_reg, test) \ No newline at end of file diff --git a/hdl/template.py.txt b/hdl/template.py.txt new file mode 100644 index 0000000..64f0655 --- /dev/null +++ b/hdl/template.py.txt @@ -0,0 +1,36 @@ +from amaranth import * +from amaranth.sim import Simulator, Settle, Delay + +from utils import cmd + +class Template(Elaboratable): + def __init__(self): + ... + + self.ports = [...] + + def elaborate(self, platform): + m = Module() + + ... + + return m + +def test(filename="out.vcd"): + dut = ... + + def proc1(): + ... + + + sim = Simulator(dut) + sim.add_clock(1e-6) + sim.add_sync_process(proc1) + + with sim.write_vcd(filename): + sim.run() + + +if __name__ == '__main__': + shift_reg = Template(...) + cmd(shift_reg, test) \ No newline at end of file -- cgit v1.2.3