added make file

4 files changed, 96 insertions, 100 deletions

diff --git a/hdl/testing/async_reset.py b/hdl/testing/async_reset.py
new file mode 100644
index 0000000..4760df7
--- /dev/null
+++ b/hdl/testing/async_reset.py
@@ -0,0 +1,21 @@
+from amaranth import *
+from amaranth.cli import main
+
+
+class ClockDivisor(Elaboratable):
+    def __init__(self, factor):
+        self.v = Signal(factor)
+        self.o = Signal()
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.sync += self.v.eq(self.v + 1)
+        m.d.comb += self.o.eq(self.v[-1])
+        return m
+
+
+if __name__ == "__main__":
+    m = Module()
+    m.domains.sync = sync = ClockDomain("sync", async_reset=True)
+    m.submodules.ctr = ctr = ClockDivisor(factor=16)
+    main(m, ports=[ctr.o, sync.clk])
\ No newline at end of file
diff --git a/hdl/testing/multi_clock.py b/hdl/testing/multi_clock.py
new file mode 100644
index 0000000..e377156
--- /dev/null
+++ b/hdl/testing/multi_clock.py
@@ -0,0 +1,75 @@
+import sys
+from amaranth import *
+from amaranth.back import verilog, cxxrtl
+from amaranth.cli import main
+from amaranth.sim import Simulator, Settle, Delay
+
+BASENAME = "multi_clock"
+
+class SubM(Elaboratable):
+    def __init__(self, domain=None):
+        self.inv = Signal()
+        self.domain=domain
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.d.sync += self.inv.eq(~self.inv)
+
+        return m
+
+class top(Elaboratable):
+    def __init__(self):
+        self.sig_slow = Signal()
+        self.sig_fast = Signal()
+
+        self.div = Signal(2)
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.domains += ClockDomain('slow')
+        m.d.sync += [self.div.eq(self.div + 1)]
+        m.d.comb += ClockSignal('slow').eq(self.div[-1])
+
+        m.submodules.subm1 = SubM()
+        m.submodules.subm2 = DomainRenamer("slow")(SubM())
+
+        m.d.sync += self.sig_fast.eq(m.submodules.subm1.inv)
+        m.d.slow += self.sig_slow.eq(m.submodules.subm2.inv)
+
+        return m
+
+def test_shift_reg():
+    dut = top()
+
+    def proc1():
+        for _ in range(16):
+            yield
+            yield Settle()
+    
+    sim = Simulator(dut)
+    sim.add_clock(1e-6)
+    sim.add_sync_process(proc1)
+    
+    with sim.write_vcd(BASENAME + '.vcd'):
+        sim.run()
+
+
+if __name__ == '__main__':
+
+    if sys.argv[1] == "sim":
+        test_shift_reg()
+        exit()
+
+    # m = ShiftReg(8)
+
+    # if sys.argv[1] == "v":
+    #     out = verilog.convert(m, ports=m.ports)
+    #     with open(BASENAME + '.v','w') as f:
+    #         f.write(out)
+    
+    # elif sys.argv[1] == "cc":
+    #     out = cxxrtl.convert(m, ports=m.ports)
+    #     with open(BASENAME + '.cc','w') as f:
+    #         f.write(out)
diff --git a/hdl/testing/shift_reg.py b/hdl/testing/shift_reg.py
deleted file mode 100644
index b7c2290..0000000
--- a/hdl/testing/shift_reg.py
+++ /dev/null
@@ -1,100 +0,0 @@
-import sys
-from amaranth import *
-from amaranth.back import verilog, cxxrtl
-from amaranth.cli import main
-from amaranth.sim import Simulator, Settle, Delay
-
-BASENAME = "shift_reg"
-
-class ShiftReg(Elaboratable):
-    def __init__(self, width):
-        self.load_val = Signal(width, reset=0, reset_less=True)
-        self.load = Signal()
-        self.reg = Signal(width)
-        self.en = Signal()
-        self.right_left = Signal()
-
-        self.ports = [self.load_val, self.en, self.right_left, self.reg]
-
-    def elaborate(self, platform):
-        m = Module()
-
-        with m.If(self.load):
-            m.d.sync += self.reg.eq(self.load_val)
-        with m.Else():
-            with m.If(self.en):
-                with m.If(self.right_left):
-                    m.d.sync += self.reg.eq(self.reg << 1)
-                with m.Else():
-                    m.d.sync += self.reg.eq(self.reg >> 1)
-
-        return m
-
-
-def step():
-    yield
-    yield Settle()
-
-def test_shift_reg():
-    dut = ShiftReg(8)
-
-    def proc1():
-        val = 0xAB
-
-        yield dut.load_val.eq(val)
-        yield dut.en.eq(0)
-        yield dut.load.eq(1)
-        yield
-        yield Settle()
-        yield dut.load.eq(0)
-        yield dut.en.eq(1)   
-
-        for _ in range(9):
-            reg_val = yield dut.reg
-            assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)}   ---GOT: {hex(reg_val)}"
-            val = val >> 1
-            yield
-            yield Settle()
-
-        val = 0xBD
-        yield dut.load_val.eq(val)
-        yield dut.load.eq(1)
-        yield dut.right_left.eq(1)
-        yield
-        yield Settle()
-        yield dut.load.eq(0)
-
-        for _ in range(9):
-            reg_val = yield dut.reg
-            assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)}   ---GOT: {hex(reg_val)}"
-            val = (val << 1) & 0xff
-            yield
-            yield Settle()
-
-
-
-    sim = Simulator(dut)
-    sim.add_clock(1e-6)
-    sim.add_sync_process(proc1)
-    
-    with sim.write_vcd(BASENAME + '.vcd'):
-        sim.run()
-
-
-if __name__ == '__main__':
-
-    if sys.argv[1] == "sim":
-        test_shift_reg()
-        exit()
-
-    m = ShiftReg(8)
-
-    if sys.argv[1] == "v":
-        out = verilog.convert(m, ports=m.ports)
-        with open(BASENAME + '.v','w') as f:
-            f.write(out)
-    
-    elif sys.argv[1] == "cc":
-        out = cxxrtl.convert(m, ports=m.ports)
-        with open(BASENAME + '.cc','w') as f:
-            f.write(out)
diff --git a/hdl/testing/v b/hdl/testing/v
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/hdl/testing/v