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authorjjsuperpower <jjs29356@gmail.com>2022-09-05 20:04:52 -0500
committerjjsuperpower <jjs29356@gmail.com>2022-09-05 20:04:52 -0500
commit63626f2f6fc7e8912a349f120e37998cd1a05554 (patch)
treea4a10c448613bd683b79a2f5dbef892edef0d49d /hdl/testing/up_counter.py
parent762e8b8786d8c921726c8ddc92a2513f42dad683 (diff)
moveing file around
Diffstat (limited to 'hdl/testing/up_counter.py')
-rw-r--r--hdl/testing/up_counter.py50
1 files changed, 0 insertions, 50 deletions
diff --git a/hdl/testing/up_counter.py b/hdl/testing/up_counter.py
deleted file mode 100644
index 050a6b0..0000000
--- a/hdl/testing/up_counter.py
+++ /dev/null
@@ -1,50 +0,0 @@
-from amaranth import *
-from amaranth.back import verilog
-
-
-class UpCounter(Elaboratable):
- """
- A 16-bit up counter with a fixed limit.
-
- Parameters
- ----------
- limit : int
- The value at which the counter overflows.
-
- Attributes
- ----------
- en : Signal, in
- The counter is incremented if ``en`` is asserted, and retains
- its value otherwise.
- ovf : Signal, out
- ``ovf`` is asserted when the counter reaches its limit.
- """
-
- def __init__(self, limit):
- self.limit = limit
-
- # Ports
- self.en = Signal()
- self.ovf = Signal()
-
- # State
- self.count = Signal(16)
-
- def elaborate(self, platform):
- m = Module()
-
- m.d.comb += self.ovf.eq(self.count == self.limit)
-
- with m.If(self.en):
- with m.If(self.ovf):
- m.d.sync += self.count.eq(0)
- with m.Else():
- m.d.sync += self.count.eq(self.count + 1)
-
- return m
-
- def to_v(self):
- return verilog.convert(self, ports=[self.en, self.ovf])
-
-top = UpCounter(25)
-print(top.to_v()) \ No newline at end of file