From 63626f2f6fc7e8912a349f120e37998cd1a05554 Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Mon, 5 Sep 2022 20:04:52 -0500 Subject: moveing file around --- hdl/testing/up_counter.py | 50 ----------------------------------------------- 1 file changed, 50 deletions(-) delete mode 100644 hdl/testing/up_counter.py (limited to 'hdl/testing/up_counter.py') diff --git a/hdl/testing/up_counter.py b/hdl/testing/up_counter.py deleted file mode 100644 index 050a6b0..0000000 --- a/hdl/testing/up_counter.py +++ /dev/null @@ -1,50 +0,0 @@ -from amaranth import * -from amaranth.back import verilog - - -class UpCounter(Elaboratable): - """ - A 16-bit up counter with a fixed limit. - - Parameters - ---------- - limit : int - The value at which the counter overflows. - - Attributes - ---------- - en : Signal, in - The counter is incremented if ``en`` is asserted, and retains - its value otherwise. - ovf : Signal, out - ``ovf`` is asserted when the counter reaches its limit. - """ - - def __init__(self, limit): - self.limit = limit - - # Ports - self.en = Signal() - self.ovf = Signal() - - # State - self.count = Signal(16) - - def elaborate(self, platform): - m = Module() - - m.d.comb += self.ovf.eq(self.count == self.limit) - - with m.If(self.en): - with m.If(self.ovf): - m.d.sync += self.count.eq(0) - with m.Else(): - m.d.sync += self.count.eq(self.count + 1) - - return m - - def to_v(self): - return verilog.convert(self, ports=[self.en, self.ovf]) - -top = UpCounter(25) -print(top.to_v()) \ No newline at end of file -- cgit v1.2.3