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| author | jjsuperpower <jjs29356@gmail.com> | 2023-01-24 22:55:15 -0600 |
|---|---|---|
| committer | jjsuperpower <jjs29356@gmail.com> | 2023-01-24 22:55:15 -0600 |
| commit | a888d4f92a5d19e4d132ea7d23c20d5f15652802 (patch) | |
| tree | 8c1e7c3f702feaa73d93421f5e8fd728cd5e4374 /hdl/core | |
| parent | 937140041c91cd2c80f3f5786b0039119dc10514 (diff) | |
fixed shift with number greater than 32
Diffstat (limited to 'hdl/core')
| -rw-r--r-- | hdl/core/alu.py | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/hdl/core/alu.py b/hdl/core/alu.py index 8693ba7..789c26e 100644 --- a/hdl/core/alu.py +++ b/hdl/core/alu.py @@ -1,4 +1,3 @@ -from cmath import exp from amaranth import * from amaranth.sim import Simulator, Settle, Delay from enum import Enum, unique @@ -94,12 +93,12 @@ class ALU(Elaboratable): with m.Case(AluOpCodes.lright.value): tmp2 = Signal(33) - m.d.comb += tmp2.eq(Cat(0, self.in1) >> self.in2[0:5]) + m.d.comb += tmp2.eq(Cat(0, self.in1) >> self.in2) m.d.comb += self.tmp.eq(Cat(tmp2[1:33], tmp2[0])) # move shifted bit to carry bit with m.Case(AluOpCodes.aright.value): tmp2 = Signal(33) - m.d.comb += tmp2.eq(Cat(0, self.in1).as_signed() >> self.in2[0:5]) + m.d.comb += tmp2.eq(Cat(0, self.in1).as_signed() >> self.in2) m.d.comb += self.tmp.eq(Cat(tmp2[1:33], tmp2[0])) # move shifted bit to carry bit with m.Case(AluOpCodes.multul.value): |