From a888d4f92a5d19e4d132ea7d23c20d5f15652802 Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Tue, 24 Jan 2023 22:55:15 -0600 Subject: fixed shift with number greater than 32 --- hdl/core/alu.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'hdl/core') diff --git a/hdl/core/alu.py b/hdl/core/alu.py index 8693ba7..789c26e 100644 --- a/hdl/core/alu.py +++ b/hdl/core/alu.py @@ -1,4 +1,3 @@ -from cmath import exp from amaranth import * from amaranth.sim import Simulator, Settle, Delay from enum import Enum, unique @@ -94,12 +93,12 @@ class ALU(Elaboratable): with m.Case(AluOpCodes.lright.value): tmp2 = Signal(33) - m.d.comb += tmp2.eq(Cat(0, self.in1) >> self.in2[0:5]) + m.d.comb += tmp2.eq(Cat(0, self.in1) >> self.in2) m.d.comb += self.tmp.eq(Cat(tmp2[1:33], tmp2[0])) # move shifted bit to carry bit with m.Case(AluOpCodes.aright.value): tmp2 = Signal(33) - m.d.comb += tmp2.eq(Cat(0, self.in1).as_signed() >> self.in2[0:5]) + m.d.comb += tmp2.eq(Cat(0, self.in1).as_signed() >> self.in2) m.d.comb += self.tmp.eq(Cat(tmp2[1:33], tmp2[0])) # move shifted bit to carry bit with m.Case(AluOpCodes.multul.value): -- cgit v1.2.3