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| author | jjsuperpower <jjs29356@gmail.com> | 2023-01-22 23:26:52 -0600 |
|---|---|---|
| committer | jjsuperpower <jjs29356@gmail.com> | 2023-01-22 23:26:52 -0600 |
| commit | 0a9a7393aaef36ee35e75cbcf0fcd77d29a046e1 (patch) | |
| tree | a0bb64b2d484049fdb69a26c919bdadcc9f26896 /hdl/config.py | |
| parent | fcabfb8f6d900a3c27f811cf345821ebe75fe70c (diff) | |
added rtlil export
Diffstat (limited to 'hdl/config.py')
| -rw-r--r-- | hdl/config.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hdl/config.py b/hdl/config.py index 989a090..0ff2bc0 100644 --- a/hdl/config.py +++ b/hdl/config.py @@ -5,6 +5,7 @@ ROOT_DIR = os.path.dirname(os.path.abspath(__file__)) HDL_PATH = os.path.join(ROOT_DIR, 'hdl') VERILOG_DIR = os.path.join(ROOT_DIR, 'gen_verilog') CXXRTL_DIR = os.path.join(ROOT_DIR, 'gen_cxxrtl') +RTLIL_DIR = os.path.join(ROOT_DIR, 'gen_rtlil') VCD_DIR = os.path.join(ROOT_DIR, 'gen_vcd') -NUM_RAND_TESTS = 250
\ No newline at end of file +NUM_RAND_TESTS = 100
\ No newline at end of file |