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authorjjsuperpower <jjs29356@gmail.com>2023-01-22 23:26:52 -0600
committerjjsuperpower <jjs29356@gmail.com>2023-01-22 23:26:52 -0600
commit0a9a7393aaef36ee35e75cbcf0fcd77d29a046e1 (patch)
treea0bb64b2d484049fdb69a26c919bdadcc9f26896 /hdl
parentfcabfb8f6d900a3c27f811cf345821ebe75fe70c (diff)
added rtlil export
Diffstat (limited to 'hdl')
-rw-r--r--hdl/config.py3
-rw-r--r--hdl/utils.py7
2 files changed, 8 insertions, 2 deletions
diff --git a/hdl/config.py b/hdl/config.py
index 989a090..0ff2bc0 100644
--- a/hdl/config.py
+++ b/hdl/config.py
@@ -5,6 +5,7 @@ ROOT_DIR = os.path.dirname(os.path.abspath(__file__))
HDL_PATH = os.path.join(ROOT_DIR, 'hdl')
VERILOG_DIR = os.path.join(ROOT_DIR, 'gen_verilog')
CXXRTL_DIR = os.path.join(ROOT_DIR, 'gen_cxxrtl')
+RTLIL_DIR = os.path.join(ROOT_DIR, 'gen_rtlil')
VCD_DIR = os.path.join(ROOT_DIR, 'gen_vcd')
-NUM_RAND_TESTS = 250 \ No newline at end of file
+NUM_RAND_TESTS = 100 \ No newline at end of file
diff --git a/hdl/utils.py b/hdl/utils.py
index 792e8a7..9c0277d 100644
--- a/hdl/utils.py
+++ b/hdl/utils.py
@@ -9,7 +9,7 @@ import random
#hdl specific imports
from amaranth import *
from amaranth import Elaboratable
-from amaranth.back import verilog, cxxrtl
+from amaranth.back import verilog, cxxrtl, rtlil
from amaranth.sim import Settle, Delay, Simulator
#custom imports
@@ -46,6 +46,11 @@ def cmd(hdl):
with open(os.path.join(CXXRTL_DIR, os.path.basename(sys.argv[0]).replace('.py', '.cc')), 'w') as f:
f.write(out)
+ elif sys.argv[1] == "rt":
+ out = rtlil.convert(hdl, ports=hdl.ports['in'] + hdl.ports['out'])
+ with open(os.path.join(RTLIL_DIR, os.path.basename(sys.argv[0]).replace('.py', '.il')), 'w') as f:
+ f.write(out)
+
def e2s(e: Enum):
'''
Get signal length from enum, returns ceil(log2(len(e))))