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import sys
from inspect import stack # get name of caller function
from typing import Callable
from amaranth import *
from amaranth import Elaboratable
from amaranth.back import verilog, cxxrtl
from amaranth.sim import Settle, Delay, Simulator
from hdl.config import *
def cmd(hdl):
'''
Very simple command line interface
The elaboratable class must have a ports attribute that is a dict of in and out ports {'in': [Signals()], 'out': [Signals()]}
'''
if len(sys.argv) <= 1:
print('Usage: v|cc v = generate verilog, cc = generate cxxrtl')
exit()
if sys.argv[1] == "sim":
# tb(sys.argv[0].replace('.py', '.vcd'))
# exit()
assert "sim option deprecated, use pytest command instead"
if sys.argv[1] == "v":
out = verilog.convert(hdl, ports=hdl.ports['in'] + hdl.ports['out'])
with open(os.path.join(VERILOG_DIR, sys.argv[0].replace('.py', '.v')), 'w') as f:
f.write(out)
elif sys.argv[1] == "cc":
out = cxxrtl.convert(hdl, ports=hdl.ports['in'] + hdl.ports['out'])
with open(os.path.join(CXXRTL_DIR, sys.argv[0].replace('.py', '.cc')), 'w') as f:
f.write(out)
def sim(dut:Elaboratable, proc: Callable):
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_sync_process(proc)
with sim.write_vcd(os.path.join(VCD_DIR, stack()[1].function + '.vcd')):
sim.run()
def step(cycles=1):
for _ in range(cycles):
yield Settle() # settle comb logic before clock
yield # clock edge
yield Settle() # settle comb logic after clock
yield Delay(5e-7) # used for debugging, change values on neg edge of clock
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