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from amaranth import *
from amaranth.sim import Simulator, Settle, Delay
from enum import Enum, unique
from hdl.utils import cmd, step, sim
from hdl.lib.in_out_buff import InOutBuff # used for timing analysis
class HDL(Elaboratable):
def __init__(self, **kargs):
...
ports_in = []
ports_out = []
self.ports = {'in': ports_in, 'out': ports_out}
self.sim = kargs["sim"] if "sim" in kargs else False
def elaborate(self, platform=None):
m = Module()
# dummy sync for simulation only needed if there is no other sequential logic
if self.sim == True:
dummy = Signal()
m.d.sync += dummy.eq(~dummy)
...
return m
# test addition
def test_hdl():
dut = HDL(sim=True)
def proc():
yield from step #step clock
yield Settle() #needed if for combinatorial logic
yield dut.something #read value
sim(dut, proc)
if __name__ == '__main__':
hdl = InOutBuff(HDL())
cmd(hdl)
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