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from amaranth import *
from amaranth.sim import Simulator, Settle, Delay
from enum import Enum, unique
from hdl.utils import cmd
# class ASAP32Core(Elaboratable):
# def __init__(self):
# self.interupt_msk = Signal(32)
# self.interupt_addr = Signal(32)
# self.interupt_en = Signal(1)
# self.interupt_sig = Signal(1)
# self.jump = Signal(1)
# self.instruction_addr = Signal(32)
# self.ports = []
# def elaborate(self, platform=None):
# m = Module()
# m.submodules.reg = reg = Reg()
# # interupt setup
# m.d.comb += self.interupt_en.eq(reg.cr[0])
# # get instruction address, account for jumps and interupts
# m.d.sync += self.instruction_addr.eq(Mux(self.interupt_en & self.interupt_sig, self.interupt_addr, Mux(self.jump, reg.ja, reg.ip)))
# # update program counter
# m.d.sync += reg.ip.eq(self.instruction_addr + 1)
# return m
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