1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
|
from amaranth import *
from amaranth.sim import Simulator, Settle, Delay
from enum import Enum, unique
from hdl.utils import *
from hdl.lib.in_out_buff import InOutBuff # used for timing analysis
from alu import AluOpCodes
from jump_ctl import JumpOpCodes
class Control(Elaboratable):
def __init__(self, **kargs):
self.instr_op = Signal(4, reset_less=True)
# out opcodes
self.alu_op = Signal(e2s(AluOpCodes))
self.jump_ctl_op = Signal(e2s(JumpOpCodes))
# register control out
self.wr_en = Signal(1)
self.stall = Signal(1)
self.int_sig = Signal(1)
self.iret = Signal(1)
self.call = Signal(1)
self.jump = Signal(1)
# register control in
self.int_en = Signal(1)
self.user_mode = Signal(1)
ports_in = [self.instr_op, self.alu_op, self.jump_ctl_op, self.wr_en, self.stall, self.int_sig, self.iret, self.call, self.jump]
ports_out = []
self.ports = {'in': ports_in, 'out': ports_out}
self.sim = kargs["sim"] if "sim" in kargs else False
def elaborate(self, platform=None):
m = Module()
# dummy sync for simulation only needed if there is no other sequential logic
if self.sim == True:
dummy = Signal()
m.d.sync += dummy.eq(~dummy)
...
return m
# test addition
def test_hdl():
dut = Control(sim=True)
def proc():
yield from step #step clock
yield Settle() #needed if for combinatorial logic
yield dut.something #read value
sim(dut, proc)
if __name__ == '__main__':
hdl = InOutBuff(Control())
cmd(hdl)
|
