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# Instruction Set Reference
This chapter describes the instruction set for the Vertex-32 and Vertex-64
architectures in V32 and V64 modes of operation. For each instruction, each
operand combination is described, a description of the effect upon the FLG
register and a summary of possible exceptions are also provided.
## Registers
Figure 3.1 shows the initial state of the registers in the ISA. For V32, the
16 registers are each 32 bits wide. Register `0X` is hardwired with all bits
equal to 0. General purpose registers `AX` to `GX` hold values that various
instructions interpret as a collection of Boolean values, or as two's
complement signed binary integers or unsigned binary integers. The registers
`PTR`, `IDTR` and `CRX` are considered privileged and writing to them in the
unprivileged state will generate a general protection fault.
## Base Instruction Formats
In the core V32 ISA, there are four instruction formats (C/I/R/J), as shown in
Figure 3.3. All are a fixed 32 bits in length and must be aligned on a four-byte
boundary in memory. An instruction alignment exception is generated if a branch
or jump instruction is called on an address that is not four-byte aligned. No
exception is generated on a branch or jump not taken.
## Integer Instructions
Most integer computational instructions operate on 32 or 64 bit values held in
a register or memory location. Integer instructions are encoded as
register-immediate operations using the I-type format or as register-register
operations using the R-type format. The destination is `RD` for both
register-immediate and register-register operations. If any of the following
instructions cause an overflow or underflow, the overflow flag is set.
### Integer-Register Instructions
The instructions that follow are operations between registers; an attempt to use
a non-register operand will result in an invalid opcode exception. The format
for these exceptions follow Figure 3.4.
#### ADD
`ADD` adds the second and third operands and stores the result in the first
operand.
#### SUB
`SUB` subtracts the third operand from the second operand and stores the result
in the first operand.
#### MUL/MULU
`MUL` multiplies the second operand by the third operand and stores the result
in the first operand. `MULU` performs the same operation on unsigned integers.
#### DIV/DIVU
`DIV` divides the second operand by the third operand. The dividend is stored in
the upper 16 bits of the first operand, and the remainder is stored in the lower
16 bits. `DIVU` performs the same operation on unsigned integers.
#### XOR
`XOR` performs a bitwise 'exclusive or' operation between the second and third
operands and stores the result in the first operand.
#### OR
`OR` performs a bitwise 'or' operation between the second and third operands and
stores the result in the first operand.
#### AND
`AND` performs a bitwise 'and' operation between the second and third operands
and stores the result in the first operand.
#### LSL
`LSL` performs a logical shift left. The second operand is shifted left by `n`
bits, where `n` is the third operand. The result is stored in the first operand.
#### LSR
`LSR` performs a logical shift right. The second operand is shifted right by
'n' bits, where 'n' is the third operand. The result is stored in the first
operand.
#### ASR
`ASR` performs an arithmetic shift right. The second operand is shifted right by
'n' bits, where 'n' is the third operand. The result is stored in the first
operand.
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