diff options
Diffstat (limited to 'hdl_lab/hdl/myhdl_wrap.py')
| -rw-r--r-- | hdl_lab/hdl/myhdl_wrap.py | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/hdl_lab/hdl/myhdl_wrap.py b/hdl_lab/hdl/myhdl_wrap.py index 2e8fe4e..56c8c5b 100644 --- a/hdl_lab/hdl/myhdl_wrap.py +++ b/hdl_lab/hdl/myhdl_wrap.py @@ -9,6 +9,22 @@ class Myhdl_Wrapper(): def _export(self, **kargs): inst = getattr(self, self.class_name)(**kargs) inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}") + + test_bench_file = GEN_VERILOG + 'tb_' +self.class_name + '.v' + test_bench_tmp_file = GEN_VERILOG + '~tb_' +self.class_name + '.v' + + # this is needed to generate cosim vcd file + with open(test_bench_file) as f_old, open(test_bench_tmp_file, 'w') as f_new: + lines = f_old.readlines() + for line in lines: + f_new.write(line) + if 'initial begin' in line: + f_new.write('\n') + f_new.write(' // Needed to create vcd file\n') + f_new.write(f' $dumpfile ("{SIM_DIR + self.class_name}_cosim.vcd");\n') + f_new.write(f' $dumpvars(0, tb_{self.class_name});\n') + f_new.write('\n') + os.rename(test_bench_tmp_file, test_bench_file) |