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-rw-r--r--hdl/testing/shift_reg.py16
-rw-r--r--hdl/testing/top.py10
2 files changed, 12 insertions, 14 deletions
diff --git a/hdl/testing/shift_reg.py b/hdl/testing/shift_reg.py
index a98fb4c..c27b0f7 100644
--- a/hdl/testing/shift_reg.py
+++ b/hdl/testing/shift_reg.py
@@ -1,9 +1,7 @@
-from fileinput import filename
from myhdl import *
+from random import randrange
import os
-from sympy import Si
-
from constants import *
class ShiftReg():
@@ -13,7 +11,7 @@ class ShiftReg():
# Main code, this is the actual logic
@staticmethod
@block
- def logic(reset: Signal, clk: Signal, in0: Signal, out0: Signal, left_rigt: bool = 1, width: int = 8):
+ def ShiftReg(reset: Signal, clk: Signal, in0: Signal, out0: Signal, left_rigt: bool = 0, width: int = 8):
@always_seq(clk.posedge, reset=reset)
def shifter():
@@ -97,7 +95,9 @@ class ShiftReg():
tb = self.tb('_cosim')
tb.run_sim()
-hdl = ShiftReg()
-hdl.sim()
-hdl.convert()
-hdl.cosim()
+
+def test_shift_reg():
+ hdl = ShiftReg()
+ hdl.sim()
+ hdl.convert()
+ hdl.cosim()
diff --git a/hdl/testing/top.py b/hdl/testing/top.py
index 55c5714..72e14cd 100644
--- a/hdl/testing/top.py
+++ b/hdl/testing/top.py
@@ -2,17 +2,15 @@ from myhdl import *
from constants import GEN_VERILOG
from shift_reg import ShiftReg
-logic = ShiftReg.logic
-
+logic = ShiftReg.ShiftReg
@block
def top(clk, reset, in0, out0):
- n0 = Signal(modbv(0)[8:])
-
+ node = Signal(modbv(0)[8:])
- sr0 = logic(clk=clk, reset=reset, in0=in0, out0=n0)
- sr1 = logic(clk=clk, reset=reset, in0=n0[7], out0=out0)
+ sr0 = logic(clk=clk, reset=reset, in0=in0, out0=node)
+ sr1 = logic(clk=clk, reset=reset, in0=node(7), out0=out0)
return sr0, sr1