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-rw-r--r--hdl/testing/Makefile12
1 files changed, 12 insertions, 0 deletions
diff --git a/hdl/testing/Makefile b/hdl/testing/Makefile
index e69de29..5e6391c 100644
--- a/hdl/testing/Makefile
+++ b/hdl/testing/Makefile
@@ -0,0 +1,12 @@
+
+HDL = shift_reg.py
+
+
+test:
+ py.test --disable-pytest-warnings -v $(HDL)
+
+test-w:
+ py.test -v $(HDL)
+
+clean:
+ $(RM) -rf simulation/* gen_verilog/* __pycache__/* .pytest_cache/* \ No newline at end of file